Patents by Inventor Satoru Machida

Satoru Machida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070269972
    Abstract: Provided is a method of manufacturing a semiconductor device having an ONO film composed of a bottom silicon oxide film, a silicon nitride film and a top silicon oxide film over a substrate. The top silicon oxide film of the ONO film is formed in the following manner. A silicon oxide film is formed over the silicon nitride film, and then a hydrogen gas and an oxygen gas are reacted over the silicon nitride film by heating the silicon nitride film (substrate) while reducing the pressure from the atmospheric pressure to grow the silicon oxide film into the top silicon oxide film. According to the present invention, a silicon oxide film having good uniformity and fewer defects can be formed over a silicon-containing underlayer.
    Type: Application
    Filed: May 4, 2007
    Publication date: November 22, 2007
    Inventors: Yoshiyuki Kawashima, Yasushi Ishii, Koichi Toba, Satoru Machida, Takashi Hashimoto
  • Publication number: 20070262382
    Abstract: In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 14 of the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrode 15 are formed in a multilayer structure including an electrode material film 8A and an electrode material layer 8B, and the gate electrode 14 is a single layer structure formed at the same time as the electrode material film 8A of the control gate.
    Type: Application
    Filed: March 27, 2007
    Publication date: November 15, 2007
    Inventors: Yasushi Ishii, Takashi Hashimoto, Yoshiyuki Kawashima, Koichi Toba, Satoru Machida, Kozo Katayama, Kentaro Saito, Toshikazu Matsui
  • Publication number: 20070228446
    Abstract: A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.
    Type: Application
    Filed: March 13, 2007
    Publication date: October 4, 2007
    Inventors: Koichi Toba, Yasushi Ishii, Yoshiyuki Kawashima, Satoru Machida, Munekatsu Nakagawa, Kentaro Saito, Toshikazu Matsui, Takashi Hashimoto, Kosuke Okuyama
  • Publication number: 20070228498
    Abstract: Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.
    Type: Application
    Filed: March 8, 2007
    Publication date: October 4, 2007
    Inventors: Koichi Toba, Yasushi Ishii, Yoshiyuki Kawashima, Satoru Machida, Munekatsu Nakagawa, Takashi Hashimoto
  • Publication number: 20070215930
    Abstract: A memory cell has a control gate electrode disposed on a main surface of a semiconductor substrate through a gate insulating film, an ONO film disposed along a side surface of the control gate electrode and the main surface of semiconductor substrate, a memory gate electrode disposed on a side surface of the control gate electrode and also on the main surface of the semiconductor substrate through the ONO film. The control gate electrode and the memory gate electrode are formed, over the upper portions thereof, with a silicide film and an insulating film formed by oxidation of the surface of the silicide film, respectively.
    Type: Application
    Filed: February 1, 2007
    Publication date: September 20, 2007
    Inventors: Satoru Machida, Yasushi Ishii, Toshio Kudo, Masato Takahashi, Yukihiro Suzuki
  • Publication number: 20060003508
    Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 5, 2006
    Inventors: Takeshi Sakai, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada