Abstract: An amplification apparatus includes a bias circuit for supplying a bias voltage, and an amplification circuit to which the bias voltage is supplied from the bias circuit. The bias circuit includes a first current source for increasing/decreasing a first current depending on the bias voltage, and a first MOSFET with first polarity through which the first current flows, to output a first voltage from a connection between the first current source and the first MOSFET; a second current source for outputting a constant current as a second current, and a second MOSFET with second polarity through which the second current flows, to output a second voltage from a connection between the second current source and the second MOSFET; and a voltage comparator for increasing/decreasing the bias voltage such that the first and second voltages become equal, based on a difference between the first and second voltages.

Abstract: An amplification apparatus includes a bias circuit for supplying a bias voltage, and an amplification circuit to which the bias voltage is supplied from the bias circuit. The bias circuit includes a first current source for increasing/decreasing a first current depending on the bias voltage, and a first MOSFET with first polarity through which the first current flows, to output a first voltage from a connection between the first current source and the first MOSFET; a second current source for outputting a constant current as a second current, and a second MOSFET with second polarity through which the second current flows, to output a second voltage from a connection between the second current source and the second MOSFET; and a voltage comparator for increasing/decreasing the bias voltage such that the first and second voltages become equal, based on a difference between the first and second voltages.

Abstract: An amplifier includes a ground, first and second MOS transistors, a first resistive load and a supply voltage, which are connected in series in this order. A bias circuit provides first and second bias voltages to the gate electrodes of the first and second transistors, respectively. The bias circuit includes a third MOS transistor having its gate and drain electrode diode-connected. The drain electrode of the third transistor provides the first bias voltage of the amplifier. The bias circuit further includes fourth and fifth MOS transistors, and a second resistive load, which are connected in series in this order. The second resistive load is connected to the supply voltage. The fourth transistor has its gate electrode connected to the drain electrode of the third transistor. The fifth transistor has its gate and drain electrodes diode-connected. The drain electrode of the fifth transistor provides the second bias voltage.

Abstract: An amplifier includes a ground, first and second MOS transistors, a first resistive load and a supply voltage, which are connected in series in this order. A bias circuit provides first and second bias voltages to the gate electrodes of the first and second transistors, respectively. The bias circuit includes a third MOS transistor having its gate and drain electrode diode-connected. The drain electrode of the third transistor provides the first bias voltage of the amplifier. The bias circuit further includes fourth and fifth MOS transistors, and a second resistive load, which are connected in series in this order. The second resistive load is connected to the supply voltage. The fourth transistor has its gate electrode connected to the drain electrode of the third transistor. The fifth transistor has its gate and drain electrodes diode-connected. The drain electrode of the fifth transistor provides the second bias voltage.

Abstract: A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

Abstract: A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

Abstract: A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

Abstract: A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

Abstract: A semiconductor memory device has memory cells storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column-data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

Abstract: A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

Abstract: A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

Abstract: A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

Abstract: A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

Abstract: Disclosed herein is a semiconductor device having a semiconductor memory circuit whose operation is tested in combination with an external test means to specify defective portions produced in a memory section of the semiconductor memory circuit and shorten the time necessary for its test.

Abstract: A semiconductor device that enables a reduction in power consumption and a stable operation, and which can be manufactured easily and with a high level of integration.In an invention exemplifying the present application, a sense circuit constituting a DRAM comprises a bit line pre-charge circuit, a pre-amplifier circuit PSA100 and a main amplifier circuit MSA100. The pre-amplifier circuit is provide with a switch circuit and an amplifier circuit. The switch circuit comprises a switch element provided between input/output terminals and a pre-sense node, and a switch element provided between input/output terminals and another pre-sense node. The amplifier circuit comprises MOS transistors and switch elements.

Abstract: A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

Abstract: According to one aspect of the invention, a semiconductor memory has, as word lines, a layer of high-resistance signal lines that are paralleled in a separate layer by low-resistance signal lines. Each high-resistance signal line is divided into segments separated by gaps. Interconnections between the high- and low-resistance signal lines in each word line are aligned with the gaps in the high-resistance signal lines in the adjacent word lines. According to a second aspect of the invention, the low-resistance signal lines extend, from alternate directions, to approximately the midpoints of the high-resistance signal lines. The high-resistance signal lines are undivided, or are divided into only two segments apiece. The high- and low-resistance signal lines are interconnected at the midpoints, or at the midpoints and one end.

Abstract: A plurality of memory cell arrays each having a plurality of memory cells and a plurality of word lines the word lines are driven by drive circuits which share the driving operation, and permit reading out from and writing into the memory cells connected to the word lines WL to be driven. These drive circuits are respectively connected to main word lines WLO, which are driven by decoding the entered address information in a decoding circuit whereby the drive circuits are driven. Since the main word lines WLO are formed with a third metal wiring layer, a wiring of the word lines can be formed with a gate wiring layer of a transistor and a first metal wiring layer and wiring of a line control circuit can be formed with a second metal wiring layer which intersects the word lines thereby reducing delay operation of the memory.

Abstract: There is provided a current amplifier and a data bus circuit using such a current amplifier capable of reducing input impedance with a smaller circuit area than the conventional so that high-speed operation of the data bus lines can be realized without a remarkable increase of the circuit area. The current amplifier includes first and second field effect transistors N11, N12 respectively provided between a pair of input terminals I, Ib and a first potential supply terminal Vcc, and third and fourth field effect transistors N13, N14 for supplying output power to a pair of output terminals O, Ob.

Abstract: A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.