Abstract: A latch circuit has two initializing circuits that receive identical inputs and generate two identical output signals, one internal and one external. An inverter inverts the internal output signal to generate a complementary external output signal. One or more control signals can force the output signals to fixed states. When the control signals are inactive, the output signals depend on either an input signal or a feedback signal generated from the internal output signal, as selected by a selecting circuit.

Abstract: A semiconductor integrated circuit has output buffers connected in parallel between one or more upper potential lines and one or more lower potential lines. Each output buffer has an output terminal coupled by first and third switching circuits to upper potential lines, and by second and fourth switching circuits to lower potential lines. In the high output state the first switching circuit is switched on, then the third switching circuit is switched on. In the low output state the second switching circuit is switched on, then the fourth switching circuit is switched on. An upper voltage threshold element switches the first switching circuit off above a first threshold output potential. A lower voltage threshold element switches the second circuit off below a second threshold output potential.

Abstract: A FET load circuit consists of two depletion-mode FETs connected in series. The gate of one FET is connected to ground. The gate of the other FET is connected to its source. This load circuit reduces power dissipation and provides superior operational stability, particularly in gallium-arsenide DCFL logic and memory circuits.

Abstract: A MOS gate array has a PLA formed in a memory area which includes a plurality of first and second elementary unit circuits. The first elementary unit circuit includes two output lines, one input line, two PMOS transistors, and four NMOS transistors. The second elementary unit circuit includes two input lines, an output line, two PMOS transistors, and four NMOS transistors. Input lines are formed to extend substantially perpendicularly to the output lines. Thus, the PLA is constructed so as to have a high degree of integration.