Abstract: A clock distributing circuit, that comprises a clock distribution output circuit for inputting an external clock, outputting a first clock that synchronizes with the external clock, and distributing the first clock to each of load circuits, and a distributed clock input circuit disposed on input stages of all or part of the load circuits and adapted for inputting the first clock and outputting a second clock that synchronizes with the input clock, wherein one of the clock distribution output circuit and the distributed clock input circuit includes a phase difference-voltage converting circuit for converting the phase difference between the input clock and the output clock into a voltage, and a voltage control type delay circuit for delaying the input clock corresponding to an output voltage of the phase difference-voltage converting circuit and for outputting the delayed input clock.

Abstract: A variable level shifter has a first transconductor cell receiving a first pair of voltages, and second and third transconductor cells both receiving a second pair of voltages. The transconductor cells are differential voltage-to-current amplifiers employing field-effect transistors. The two current outputs of the first transconductor cell are coupled to respective output terminals. One current output of the second transconductor cell is coupled to one of these output terminals, and the corresponding current output of the third transconductor cell is coupled to the other output terminal. A fourth transconductor cell may be added to obtain two pairs of outputs shifted in opposite directions. A differential multiplier can be constructed using this four-cell variable level shifter and additional field-effect transistors.

Abstract: A bias circuit with low sensitivity to threshold variations provides a bias voltage independent of transistor threshold variations and also a bias voltage independent of source potential variation. Negative feedback controls the bias voltage at one output.

Abstract: According to one aspect of the invention, a semiconductor memory has, as word lines, a layer of high-resistance signal lines that are paralleled in a separate layer by low-resistance signal lines. Each high-resistance signal line is divided into segments separated by gaps. Interconnections between the high- and low-resistance signal lines in each word line are aligned with the gaps in the high-resistance signal lines in the adjacent word lines. According to a second aspect of the invention, the low-resistance signal lines extend, from alternate directions, to approximately the midpoints of the high-resistance signal lines. The high-resistance signal lines are undivided, or are divided into only two segments apiece. The high- and low-resistance signal lines are interconnected at the midpoints, or at the midpoints and one end.

Abstract: There is provided a level shifter circuit which operates such that when the potential of the input signal changes from the ground potential to the first power source potential, the third transistor turns to be ON, and the fifth transistor turns to be OFF. On this instance, since the potential of the output signal is higher than the first power source potential, the second electrode of the first transistor is initiated to be charged up through the third and the fourth transistors. After that, the potential of the output signal falls down when the eighth transistor turns to be ON state. Since the potential of the second electrode of the first transistor has been charged up, the second transistor quickly turns to be OFF state so that the rush current is reduced flown from the second power source potential to the ground potential.

Abstract: An object of the present invention is to provide a buffer circuit little sensitive to a deviation from a threshold voltage of each of transistors. In order to achieve the above object, the present invention provides a typical buffer circuit comprising the following components.

Abstract: A digital signal transmission circuit for transmitting an input pulse signal to receiving circuits through transmission lines. The digital signal transmission circuit is provided with a phase converting circuit for outputting a first output signal and a second output signal delayed in phase with respect to the first output signal according to the input of the pulse signal, a first transmission line included in the transmission lines, for transmitting the first output signal, a second transmission line included in the transmission lines, for transmitting the second output signal, and a pair of phase decoding circuits for receiving the first and second output signals from the first and second transmission lines and outputting pulse signals according to the state of reception of the first and second output signals.

Abstract: A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.

Abstract: A semiconductor memory device includes a memory cell array for storing information and parity bits, a register circuit for temporarily holding the information and parity bits in respective bit register circuits, and an XOR circuit for detecting an error of logical values of the information and parity bits in accordance with a predetermined verifying matrix. The XOR circuit includes a plurality of XORs each having an input line pair for receiving information in a first direction, an input line pair for receiving information in a second direction perpendicular to the first direction, and an output line pair outputting XOR logical values in the second direction.

Abstract: A dynamic RAM having a TAG address holding circuit in a TAG block in correspondence with one of a plurality of sub-arrays to hold the lower bits of an X (row) address. A block control circuit in the TAG block determines a "Hit" or "Miss" in accordance with the held address and a new X address in response to the sub-address and outputs a TAG determination signal. In response to the TAG judgment signal, a sub-array control circuit transfers a signal for access to the TAG block and a column sense amplifier. The column sense amplifier is utilized as a cache and data latched in the column sense amplifier are read out on a data bus when a "Hit" is determined.

Abstract: A digital signal transmission circuit for transmitting an input pulse signal to receiving circuits through transmission lines. The digital signal transmission circuit is provided with a phase converting circuit for outputting a first output signal and a second output signal delayed in phase with respect to the first output signal according to the input of the pulse signal, a first transmission line included in the transmission lines, for transmitting the first output signal, a second transmission line included in the transmission lines, for transmitting the second output signal, and a pair of phase decoding circuits for receiving the first and second output signals from the first and second transmission lines and outputting pulse signals according to the state of reception of the first and second output signals.

Abstract: A Schmitt trigger circuit has a field effect transistor coupled between a first fixed potential and an output terminal, and a variable negative resistance circuit coupled between the output terminal and a second fixed potential; the gate of the field effect transistor and the control input of the negative resistance circuit are coupled to the input terminal of the Schmitt trigger circuit; wherein the negative resistance circuit includes a first field effect transistor coupled between the output terminal and the second fixed potential, and a gate coupled to an internal node; a second field effect transistor coupled between the internal node and the second fixed potential, and a gate coupled to the input terminal; and a third field effect transistor coupled between the first fixed potential and the internal node, and a gate coupled to the output terminal.

Abstract: A sense circuit has input and output terminals coupled through resistances to two fixed potentials. The input potential is amplified and inverted to control the gate of a field-effect transistor coupled between the input and output terminals. Alternatively, a sense circuit has first and second input terminals, and first and second output terminals. The first input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the second input and output terminals. The second input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the first input and output terminals. The depletion-mode field-effect transistors may be replaced by negative-resistance circuits. These sense circuits can obtain large voltage outputs from small current inputs.

Abstract: A load circuit which can tolerates large current and voltage swings before saturation begins includes a field effect transistor having a source coupled to a power supply, a drain coupled to an input terminal which receives signals from a memory circuit data line, and a gate coupled to the drain through a level shifter.

Abstract: A semiconductor memory device according to the present invention is constructed in such a manner that two first and second memory circuits are respectively electrically connected to one sense amplifier provided between the memory circuits through changeover elements and equalize elements are electrically connected to their corresponding bit line pairs included in the memory circuits. Owing to this construction, an operation for resetting the bit line pair in the first memory circuit and the sense amplifier after completion of access to the first memory circuit and an operation for reading data into the bit line pair in the second memory circuit can be performed so as to overlap each other in time. It is therefore possible to obtain quick-access to the second memory circuit.

Abstract: A sense circuit has input and output terminals coupled through resistances to two fixed potentials. The input potential is amplified and inverted to control the gate of a field-effect transistor coupled between the input and output terminals. Alternatively, a sense circuit has first and second input terminals, and first and second output terminals. The first input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the second input and output terminals. The second input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the first input and output terminals. The depletion-mode field-effect transistors may be replaced by negative-resistance circuits. These sense circuits can obtain large voltage outputs from small current inputs.

Abstract: A level shifter includes an N-channel enhancement-mode field effect transistor (40), a P-channel depletion-mode field effect transistor (38), and a current mirror (42) coupled to the source of the enhancement-mode transistor and the drain of the depletion-mode transistor; wherein the gates of the transistors are coupled to an input terminal and the source of the enhancement-mode FET is coupled to an output terminal to provide a level shifted output signal.

Abstract: An inverting amplifier includes a negative resistance circuit coupled between an output node and a power supply to provide a variable negative resistance in response to an input potential, and a resistance element connected between the output node and ground.

Abstract: A clock circuit for supplying an output clock signal to a logic circuit, includes a phase difference-to-voltage converter producing a voltage signal corresponding to a phase difference between a basic clock signal and a feedback clock signal, a voltage-controlled phase controller controlled by the voltage signal from the phase difference-to-voltage converter and outputting a first clock signal, a clock supply circuit receiving the first clock signal, and supplying a second clock signal, as the output clock signal, through to the logic: circuit, a dummy clock circuit having a dummy capacitance circuit, receiving the first clock signal, and outputting a third clock signal, and a selector selectively supplying the phase difference-to-voltage converter, with a selected one of the output of the clock supply circuit and the output of the dummy clock circuit, as the feedback clock signal.

Abstract: An output buffer circuit has a pull-up output transistor controlled by a first node and a pull-down output transistor controlled by a second node. The first node is coupled to the second node through a switching stage controlled by feedback from the output terminal. When the output buffer circuit is switched between the high and low output states, the switching stage is initially on, switches off shortly after the potential of the output terminal begins to change, then switches on again when the output terminal reaches a certain intermediate potential.