Patents by Inventor Satoru Tomekawa

Satoru Tomekawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10707360
    Abstract: A thermosetting electroconductive paste composition includes an electroconductive powder (A) containing at least one of a silver-coated metal powder (A-1) and a powder of either copper or an alloy thereof (A-2), a thermosetting ingredient (B) containing at least one of an epoxy resin (B-1) and a blocked polyisocyanate compound (B-2), a hardener (C), and an alkyl- or alkenylsuccinic acid compound (D) which is a succinic acid or derivative thereof having an alkyl or alkenyl group having a carbon number of from 8 to 24 introduced into an ?-position. An amount of the alkyl- or alkenylsuccinic acid compound is 0.01 to 1.8 parts by mass per 100 parts by mass of a sum of the electroconductive powder (A) and the thermosetting ingredient (B).
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: July 7, 2020
    Assignee: KYOTO ELEX CO., LTD.
    Inventors: Toyoharu Matsubara, Satoru Tomekawa, Takamitsu Arai, Yuta Motohisa, Kimika Gotou
  • Publication number: 20190013422
    Abstract: A thermosetting electroconductive paste composition includes an electroconductive powder (A) containing at least one of a silver-coated metal powder (A-1) and a powder of either copper or an alloy thereof (A-2), a thermosetting ingredient (B) containing at least one of an epoxy resin (B-1) and a blocked polyisocyanate compound (B-2), a hardener (C), and an alkyl- or alkenylsuccinic acid compound (D) which is a succinic acid or derivative thereof having an alkyl or alkenyl group having a carbon number of from 8 to 24 introduced into an ?-position. An amount of the alkyl- or alkenylsuccinic acid compound is 0.01 to 1.8 parts by mass per 100 parts by mass of a sum of the electroconductive powder (A) and the thermosetting ingredient (B).
    Type: Application
    Filed: July 3, 2018
    Publication date: January 10, 2019
    Applicant: KYOTO ELEX CO., LTD.
    Inventors: Toyoharu MATSUBARA, Satoru TOMEKAWA, Takamitsu ARAI, Yuta MOTOHISA, Kimika GOTOU
  • Patent number: 8604350
    Abstract: A multilayer wiring board includes an insulating resin layer, wirings laid on their respective opposite surfaces of the insulating resin layer, and a via-hole conductor for electrically connecting the wirings. The via-hole conductor includes metal and resin portions. The metal portion includes first metal regions including a joined unit made of copper particles for connecting the wirings, second metal regions mainly composed of, for example, tin, a tin-copper alloy, or a tin-copper intermetallic compound, and third metal regions mainly composed of bismuth and in contact with the second metal regions. The copper particles forming the joined unit are in plane contact with one another to form plane contact portions, and the second metal regions at least partially are in contact with the first metal regions.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: December 10, 2013
    Assignee: Panasonic Corporation
    Inventors: Tsuyoshi Himori, Shogo Hirai, Hiroyuki Ishitomi, Satoru Tomekawa, Yutaka Nakayama
  • Patent number: 8563872
    Abstract: A wiring board includes a plurality of wirings laid via an insulating resin layer, and a via-hole conductor provided for electrically connecting the wirings. The via-hole conductor includes metal and resin portions. The metal portion includes a region made of copper particles, a first metal region mainly composed of tin, a tin-copper alloy, or a tin-copper intermetallic compound, and a second metal region mainly composed of bismuth, and has Cu/Sn of from 1.59 to 21.43. The copper particles are in contact with one another, thereby electrically connecting the wirings, and at least part of the first metal region covers around and extends over the portions where the copper particles are in plane contact with one another.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: October 22, 2013
    Assignees: Panasonic Corporation, Kyoto Elex Co., Ltd.
    Inventors: Shogo Hirai, Hiroyuki Ishitomi, Tsuyoshi Himori, Satoru Tomekawa, Yutaka Nakayama
  • Publication number: 20130068513
    Abstract: Disclosed is a multilayer wiring board having via-hole conductors, the via-hole conductor including a metal portion and a resin portion. The metal portion includes a first metal region which includes a link of copper particles forming a path electrically connecting a first wiring and a second wiring; a second metal region mainly composed of a metal selected from the group consisting of tin, a tin-copper alloy, and a tin-copper intermetallic compound; a third metal region mainly composed of bismuth; and a fourth metal region composed of tin-bismuth solder particles. The link has plane-to-plane contact portions where the copper particles are in plane-to-plane contact with one another. At least a part of the second metal region is in contact with the first metal region. The tin-bismuth solder particles, each surrounded by the resin portion, are interspersed in the via-hole conductor.
    Type: Application
    Filed: December 19, 2011
    Publication date: March 21, 2013
    Applicants: KYOTO ELEX CO., LTD., PANASONIC CORPORATION
    Inventors: Shogo Hirai, Tsuyoshi Himori, Hiroyuki Ishitomi, Takayuki Higuchi, Satoru Tomekawa, Yutaka Nakayama
  • Publication number: 20130008698
    Abstract: A multilayer wiring board having via-hole conductors which electrically connects a plurality of wirings arranged in a manner such that an insulating resin layer is placed between the wirings, wherein: the via-hole conductors each include copper, tin, and bismuth, namely, a first metal region including a link of copper particles in plane-to-plane contact with one another, the link electrically connecting the wirings, a second metal region mainly composed of one or more of tin, a tin-copper alloy, and a tin-copper intermetallic compound, and a third metal region mainly composed of bismuth; at least a part of the second metal region is in contact with the surface of the copper particles, the surface excluding the area of the plane-to-plane contact portion of the link; and the Cu, Sn, and Bi in the metal portion are of a composition having a specific weight ratio (Cu:Sn:Bi).
    Type: Application
    Filed: December 6, 2011
    Publication date: January 10, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Tsuyoshi Himori, Shogo Hirai, Takayuki Higuchi, Satoru Tomekawa, Yutaka Nakayama
  • Publication number: 20110290549
    Abstract: A wiring board includes a plurality of wirings laid via an insulating resin layer, and a via-hole conductor provided for electrically connecting the wirings. The via-hole conductor includes metal and resin portions. The metal portion includes a region made of copper particles, a first metal region mainly composed of tin, a tin-copper alloy, or a tin-copper intermetallic compound, and a second metal region mainly composed of bismuth, and has Cu/Sn of from 1.59 to 21.43. The copper particles are in contact with one another, thereby electrically connecting the wirings, and at least part of the first metal region covers around and extends over the portions where the copper particles are in plane contact with one another.
    Type: Application
    Filed: February 22, 2011
    Publication date: December 1, 2011
    Inventors: Shogo Hirai, Hiroyuki Ishitomi, Tsuyoshi Himori, Satoru Tomekawa, Yutaka Nakayama
  • Publication number: 20110278051
    Abstract: A multilayer wiring board includes an insulating resin layer, wirings laid on their respective opposite surfaces of the insulating resin layer, and a via-hole conductor for electrically connecting the wirings. The via-hole conductor includes metal and resin portions. The metal portion includes first metal regions including a joined unit made of copper particles for connecting the wirings, second metal regions mainly composed of, for example, tin, a tin-copper alloy, or a tin-copper intermetallic compound, and third metal regions mainly composed of bismuth and in contact with the second metal regions. The copper particles forming the joined unit are in plane contact with one another to form plane contact portions, and the second metal regions at least partially are in contact with the first metal regions.
    Type: Application
    Filed: February 22, 2011
    Publication date: November 17, 2011
    Inventors: Tsuyoshi Himori, Shogo Hirai, Hiroyuki Ishitomi, Satoru Tomekawa, Yutaka Nakayama
  • Patent number: 8012801
    Abstract: A flip chip mounting process includes the steps of supplying a resin (13) containing solder powder and a convection additive (12) onto a wiring substrate (10) having a plurality of electrode terminals (II), then bringing a semiconductor chip (20) having a plurality of connecting terminals (11) into contact with a surface of the supplied resin (13), and then heating the wiring substrate (10) to a temperature that enables the solder powder to melt. The heating step is carried out at a temperature that is higher than the boiling point of the convection additive (12) to allow the boiling convection additive (12) to move within the resin (12). During this heating step, the melted solder powder is allowed to self-assemble into the region between each electrode terminal (11) of the wiring substrate (10) and each connecting terminal (21) of the semiconductor chip to form an electrical connection between each electrode terminal (11) and each connecting terminal (21).
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: September 6, 2011
    Assignee: Panasonic Corporation
    Inventors: Seiji Karashima, Yoshihisa Yamashita, Satoru Tomekawa, Takashi Kitae, Seiichi Nakatani
  • Patent number: 7969741
    Abstract: It is intended to provide a substrate structure ensuring a shielding property and a heat discharge property of a resin part that collectively covers a plurality of electronic components and capable of downsizing, thinning, and a reduction in number of components. The substrate structure 20 of the first embodiment is provided with a substrate 21, a plurality of electronic components 22 mounted along the substrate 21, and a resin part 25 that covers the electronic components 22 and is in close contact with the substrate 21. In the substrate structure 20, the resin part 25 is provided with a reinforcing heat discharge layer 26 covering the electronic components 22 and having a heat conductivity and a reinforcing property and a shield layer 27 covering the reinforcing heat discharge layer 26, and a surface o28 of the shield layer 27 is formed into a predetermined shape corresponding to a surface structure of the display device 30 adjacent to the resin part 25.
    Type: Grant
    Filed: February 20, 2006
    Date of Patent: June 28, 2011
    Assignee: Panasonic Corporation
    Inventors: Haruo Hayakawa, Masahiro Ono, Seiji Yamaguchi, Yoshihiro Uda, Kazuhiro Shinchi, Satoru Tomekawa, Kiyoshi Nakanishi, Kosuke Kubota, Atsushi Katagiri, Motohisa Kotani, Kazuhiro Konishi, Eiji Nishimura, Takeo Matsuki
  • Patent number: 7799607
    Abstract: A process for forming bumps wherein a plurality of fine bumps are uniformly formed with high productivity. In this process, a resin (13) including solder powder and a convection additive (12) is supplied onto a substrate (10) having a plurality of electrodes (11) thereon. And subsequently the substrate (10) is heated to a temperature that enables the solder powder to melt while keeping a flat plate (14) in contact with a surface of the supplied resin (13). During this heating step, the molten solder powder is allowed to self-assemble onto the electrodes (11) so that a plurality of solder balls, resulting from the grown molten solder powder, are concurrently formed on the electrodes (11) in self-alignment manner. Finally, the flat plate (14) is moved away from the surface of the supplied resin (13), and then the resin (13) is removed to provide a substrate (10) having bumps (16) formed on the plurality of the electrodes.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Seiji Karashima, Yoshihisa Yamashita, Satoru Tomekawa, Takashi Kitae, Seiichi Nakatani
  • Patent number: 7773386
    Abstract: A flexible substrate includes: (i) a film; (ii) an insulating resin layer formed on each of a front face of the film and a rear face of the film, which rear face is opposite to the front face; (iii) a front-sided wiring pattern embedded in the insulating resin layer formed on the front face of the film, and a rear-sided wiring pattern embedded in the insulating resin layer formed on the rear face of the film; and (iv) a via which is located between the front-sided wiring pattern and the rear-sided wiring pattern and serves to electrically interconnect the front-sided wiring pattern and the rear-sided wiring pattern, wherein the insulating resin layer formed on each of the front face and the rear face of the film is thicker than the film.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: August 10, 2010
    Assignee: Panasonic Corporation
    Inventors: Yoshihisa Yamashita, Toshio Fujii, Seiichi Nakatani, Takashi Ichiryu, Satoru Tomekawa, Hiroki Yabe
  • Patent number: 7759162
    Abstract: A flip chip mounting process includes the steps of supplying a resin (13) containing solder powder and a convection additive (12) onto a wiring substrate (10) having a plurality of electrode terminals (11), then bringing a semiconductor chip (20) having a plurality of connecting terminals (11) into contact with a surface of the supplied resin (13), and then heating the wiring substrate (10) to a temperature that enables the solder powder to melt. The heating step is carried out at a temperature that is higher than the boiling point of the convection additive (12) to allow the boiling convection additive (12) to move within the resin (12). During this heating step, the melted solder powder is allowed to self-assemble into the region between each electrode terminal (11) of the wiring substrate (10) and each connecting terminal (21) of the semiconductor chip to form an electrical connection between each electrode terminal (11) and each connecting terminal (21).
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: July 20, 2010
    Assignee: Panasonic Corporation
    Inventors: Seiji Karashima, Yoshihisa Yamashita, Satoru Tomekawa, Takashi Kitae, Seiichi Nakatani
  • Patent number: 7752749
    Abstract: One of an electrode terminal of an electronic component and a connecting terminal of a wiring substrate is provided with solder beforehand, one of the wiring substrate and the electronic component is secured, and the electrode terminal and the connecting terminal are made to abut each other so that one of the wiring substrate and the electronic component, whichever is not secured, is held. The electronic component is heated so that the solder melts, and the solder is solidified while the electronic component is held, so that the electrode terminal and the connecting terminal are bonded to each other by the solder. Further, while an interval formed between the wiring substrate and the electronic component by the melted solder is being held, the electrode terminal and the connecting terminal are finely moved relative to each other with reference to a surface of the wiring substrate in an XY? direction.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: July 13, 2010
    Assignee: Panasonic Corporation
    Inventors: Tsukasa Shiraishi, Yukihiro Ishimaru, Shinobu Masuda, Satoru Tomekawa
  • Publication number: 20100148376
    Abstract: A flip chip mounting process includes the steps of supplying a resin (13) containing solder powder and a convection additive (12) onto a wiring substrate (10) having a plurality of electrode terminals (11), then bringing a semiconductor chip (20) having a plurality of connecting terminals (11) into contact with a surface of the supplied resin (13), and then heating the wiring substrate (10) to a temperature that enables the solder powder to melt. The heating step is carried out at a temperature that is higher than the boiling point of the convection additive (12) to allow the boiling convection additive (12) to move within the resin (12). During this heating step, the melted solder powder is allowed to self-assemble into the region between each electrode terminal (11) of the wiring substrate (10) and each connecting terminal (21) of the semiconductor chip to form an electrical connection between each electrode terminal (11) and each connecting terminal (21).
    Type: Application
    Filed: March 4, 2010
    Publication date: June 17, 2010
    Inventors: Seiji Karashima, Yoshihisa Yamashita, Satoru Tomekawa, Takashi Kitae, Seiichi Nakatani
  • Publication number: 20100044100
    Abstract: A substrate structure whereby a resin part for coating a plurality of electronic components by one operation is given a shielding property and the mounting strength of electronic components with respect to the substrate is secured and an electronic device including the substrate structure are provided. A substrate structure 10 includes a substrate 11, a plurality of electronic components 12 mounted along the substrate 11, and a resin part 13 coating each electronic component 12 with a resin 18 while kept in close contact with the substrate 11. The substrate structure 10 includes a frame body 15 surrounding each electronic component 12 while kept in close contact with the substrate 11 and a lid part 17 closing an opening 16 in the frame body 15, and a resin 18 is filled inside the frame body 15.
    Type: Application
    Filed: August 3, 2006
    Publication date: February 25, 2010
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masahiro Ono, Yosihiro Uda, Seiji Yamaguchi, Kazuhiro Shinchi, Satoru Tomekawa
  • Publication number: 20100020497
    Abstract: It is intended to provide a substrate structure ensuring a shielding property and a heat discharge property of a resin part that collectively covers a plurality of electronic components and capable of downsizing, thinning, and a reduction in number of components. The substrate structure 20 of the first embodiment is provided with a substrate 21, a plurality of electronic components 22 mounted along the substrate 21, and a resin part 25 that covers the electronic components 22 and is in close contact with the substrate 21. In the substrate structure 20, the resin part 25 is provided with a reinforcing heat discharge layer 26 covering the electronic components 22 and having a heat conductivity and a reinforcing property and a shield layer 27 covering the reinforcing heat discharge layer 26, and a surface o28 of the shield layer 27 is formed into a predetermined shape corresponding to a surface structure of the display device 30 adjacent to the resin part 25.
    Type: Application
    Filed: February 20, 2006
    Publication date: January 28, 2010
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Haruo Hayakawa, Masahiro Ono, Seiji Yamaguchi, Yoshihiro Uda, Kazuhiro Shinchi, Satoru Tomekawa, Kiyoshi Nakanishi, Kosuke Kubota, Atsushi Katagiri, Motohisa Kotani, Kazuhiro Konishi, Eiji Nishimura, Takeo Matsuki
  • Patent number: 7531754
    Abstract: A flexible substrate comprises a film, a first insulating resin layer on a front face of the film, a second insulating resin layer on a rear face of the film, a front-sided wiring pattern embedded in the first insulating resin layer, and a rear-sided wiring pattern embedded in the second insulating resin layer. A surface of the front-sided wiring pattern is flush with a surface of the first insulating resin layer, and a surface of the rear-sided wiring pattern is flush with a surface of the second insulating resin layer. A part of at least one of the front-sided wiring pattern and the rear-sided wiring pattern is dented toward a part of the other of the at least one of the front-sided wiring pattern and the rear-sided wiring pattern such that a portion of the front-sided wiring pattern and a portion of the rear-sided wiring pattern are jointed to each other to form a junction.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: May 12, 2009
    Assignee: Panasonic Corporation
    Inventors: Yoshihisa Yamashita, Hiroki Yabe, Takashi Ichiryu, Seiichi Nakatani, Satoru Tomekawa, Toshio Fujii, Seiji Karashima
  • Patent number: 7522938
    Abstract: Based on information indicating the signal transmission amount between the first and second circuit blocks, a switching device switches an optical signal communication form which uses a first and second optical signal transmitting/receiving devices and an electric signal communication form which uses a first and second electric signal transmitting/receiving devices. Thereby, in a portable information terminal apparatus with a separate main body operation unit and a separate screen display unit, power consumed by the optical signal communication can be suppressed.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: April 21, 2009
    Assignee: Panasonic Corporation
    Inventors: Yoshihiro Tomita, Yasushi Nakagiri, Tsuguhiro Korenaga, Kunio Hibino, Seiji Karashima, Satoru Tomekawa
  • Publication number: 20090049687
    Abstract: [Problem] To improve productivity and reliability in mounting an electronic component. [Means for Solving Problems] At least one of an electrode terminal of an electronic component and a connecting terminal of a wiring substrate is provided with solder beforehand, one of the wiring substrate and the electronic component is secured, and the electrode terminal of the electronic component and the connecting terminal of the wiring substrate are made to abut each other in a state where one of the wiring substrate and the electronic component, whichever is not secured, is held. Then, the electronic component is heated so that the solder is melted, and the solder is solidified while the electronic component is held, so that the electrode terminal and the connecting terminal are bonded to each other by means of the solder.
    Type: Application
    Filed: March 17, 2006
    Publication date: February 26, 2009
    Inventors: Tsukasa Shiraishi, Yukihiro Ishimaru, Shinobu Masuda, Satoru Tomekawa