Patents by Inventor Satoru Yamada

Satoru Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180301456
    Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.
    Type: Application
    Filed: November 22, 2017
    Publication date: October 18, 2018
    Inventors: Min Hee Cho, Jun Soo Kim, Hui Jung Kim, Tae Yoon An, Satoru Yamada, Won Sok Lee, Nam Ho Jeon, Moon Young Jeong, Ki Jae Hur, Jae Ho Hong
  • Publication number: 20180294264
    Abstract: A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction. The first and third active regions partially overlap in the second direction, and a device isolation film is configured to define the first to third active regions.
    Type: Application
    Filed: November 30, 2017
    Publication date: October 11, 2018
    Inventors: Seung Uk Han, Taek Yong Kim, Satoru Yamada, Jun Hee Lim, Ki Jae Hur
  • Patent number: 10096344
    Abstract: A holding frame for an electronic device that is to be inserted and extracted into and from a pair of grooves formed in a chassis so as to face each other, the holding frame includes a pair of plates that are parallel to each other and that form portions of the holding frame, the portions extending along the grooves, three protrusions that are arranged along the grooves and that protrude from the plates toward the grooves, and two support portions that are arranged at portions of the holding frame each of which corresponds to a center portion between a corresponding two of the three protrusions, the two support portions supporting the electronic device between the plates and the electronic device.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 9, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Shinichirou Okamoto, Shinichirou Kouno, Satoru Yamada, Atsushi Yamaguchi
  • Patent number: 10032780
    Abstract: A semiconductor device may include a plurality of dummy wirings formed on a substrate at different vertical levels and electrically floated and a plurality of dummy contact plugs each electrically connected between two adjacent dummy wirings of the plurality of dummy wiring of the plurality of dummy wirings. No dummy wiring of the plurality of dummy wirings is electrically connected to a terminal of any one of a plurality of transistors included in the substrate.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Hee Cho, Satoru Yamada, Sung-Sam Lee, Jung-Bun Lee
  • Publication number: 20180197580
    Abstract: A holding frame for an electronic device that is to be inserted and extracted into and from a pair of grooves formed in a chassis so as to face each other, the holding frame includes a pair of plates that are parallel to each other and that form portions of the holding frame, the portions extending along the grooves, three protrusions that are arranged along the grooves and that protrude from the plates toward the grooves, and two support portions that are arranged at portions of the holding frame each of which corresponds to a center portion between a corresponding two of the three protrusions, the two support portions supporting the electronic device between the plates and the electronic device.
    Type: Application
    Filed: December 21, 2017
    Publication date: July 12, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Shinichirou OKAMOTO, Shinichirou Kouno, Satoru Yamada, Atsushi Yamaguchi
  • Patent number: 10018927
    Abstract: An electroconductive member of the present invention includes an electroconductive support layer and a surface layer formed on the circumference of the electroconductive support layer and having a network structure containing an electroconductive fiber, and the electroconductive fiber has ion conductivity, and has an arithmetic mean value of top 10% fiber diameters of 0.2 ?m or more and 15.0 ?m or less. The surface layer always satisfies specific conditions.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: July 10, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Satoru Yamada, Kazuhiro Yamauchi, Norifumi Muranaka, Tetsuo Hino, Yuichi Kikuchi
  • Publication number: 20180188666
    Abstract: An electrophotographic roller includes an electro-conductive shaft core including a metallic layer at its surface, and an elastic layer on the shaft core. When kinetic friction coefficients of an outer peripheral surface of each end portion of the shaft core with respect to polyester resin are measured for one rotation of the shaft core, an average value pr of the kinetic friction coefficients is 0.05 to 0.50. When each outer peripheral surface is divided into three equal ranges, defined as a region A1, a region A2, and a region A3, in a peripheral direction of the shaft core, each of the regions has a location where the kinetic friction coefficients fall within a range of 1.5 ?r to 1.8 ?r, and a location where the kinetic friction coefficients fall within a range of 0.2 ?r to 0.5 ?r.
    Type: Application
    Filed: June 23, 2016
    Publication date: July 5, 2018
    Inventors: Satoru Yamada, Toshiro Suzuki, Yuya Tomomizu, Toshimitsu Nakazawa
  • Publication number: 20180158918
    Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.
    Type: Application
    Filed: January 11, 2018
    Publication date: June 7, 2018
    Inventors: Dongjin LEE, Junsoo KIM, Moonyoung JEONG, Satoru YAMADA, Dongsoo WOO, Jiyoung KIM
  • Publication number: 20180158826
    Abstract: A semiconductor memory device includes a substrate having an active region, word lines extending across the active region, a bit line on the active region between the word lines, a bit line node contact between the bit line and the active region, and a storage node contact on an end portion of the active region, wherein one or more of the bit line node contact or the storage node contact include silicon germanium.
    Type: Application
    Filed: July 27, 2017
    Publication date: June 7, 2018
    Inventors: Min Hee CHO, Satoru YAMADA, Junsoo KIM, Honglae PARK, Wonsok LEE, Namho JEON
  • Patent number: 9971433
    Abstract: The object of the present invention is to provide a touch panel member that is excellent in terms of suppression of visibility of a transparent electrode and has low total reflection for visible light, and a touch panel and a touch panel display device having the touch panel member. The touch panel member of the present invention comprises, in order, at least a transparent substrate, a transparent electrode, and a protective layer provided so as to cover the transparent electrode, the protective layer comprising three or more layers having different refractive indices, all of the different refractive index layers of the protective layer satisfying a specific expression, and the protective layer satisfying another specific expression.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: May 15, 2018
    Assignee: FUJIFILM Corporation
    Inventors: Takeshi Ando, Hideyuki Nakamura, Shigekazu Suzuki, Satoru Yamada, Kentarou Toyooka
  • Publication number: 20180108662
    Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.
    Type: Application
    Filed: December 7, 2017
    Publication date: April 19, 2018
    Inventors: Min Hee Cho, Woo Song Ahn, Min Su Choi, Satoru Yamada, Jun Soo Kim, Sung Sam Lee
  • Publication number: 20180061558
    Abstract: A terminal plate member on which a terminal of a coil component is mounted including: an annular frame having an inner peripheral edge; a pair of extension members extending from the inner peripheral edge of the annular frame toward an inner space of the annular frame member in a first direction; and a deformable section provided in the annular frame at proximal end of one of the pair of extension members, the deformable section having a more easily deformable property than other sections of the annular frame when force is applied. The deformable section is provided along at least an entire width in a second direction of the one of the pair of extension members. The second direction is perpendicular to the first direction.
    Type: Application
    Filed: July 28, 2017
    Publication date: March 1, 2018
    Inventors: Yoshiyuki TAHARA, Teruaki TANAKA, Akihiko NAKAMURA, Satoru YAMADA, Mitsugu KAWARAI
  • Patent number: 9905659
    Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: February 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongjin Lee, Junsoo Kim, Moonyoung Jeong, Satoru Yamada, Dongsoo Woo, Jiyoung Kim
  • Patent number: 9905768
    Abstract: Provided is a semiconductor device which includes a semiconductor layer and an insulating layer adjacent to the semiconductor layer, in which the insulating layer is formed of a crosslinked product of a polymer compound that has a repeating unit (IA) represented by the following Formula (IA) and a repeating unit (IB) represented by the following Formula (IB); and an insulating layer-forming composition which is used for forming an insulating layer of a semiconductor device and contains a polymer compound that has the following repeating units (IA) and (IB). In Formulae, R1a and R1b each independently represent a hydrogen atom, a halogen atom, or an alkyl group. L1a, L2a, and L1b each independently represent a single bond or a linking group. X represents a crosslinkable group and YB represents a decomposable group or a hydrogen atom. m1a and m2a each independently represent an integer of 1 to 5. The symbol “*” represents a bonding position of the repeating units.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: February 27, 2018
    Assignee: FUJIFILM Corporation
    Inventors: Yuzo Nagata, Hiroo Takizawa, Satoru Yamada
  • Publication number: 20180039201
    Abstract: Provided is such a conductive member that a change in its electrical resistance value caused by its long-term use is reduced to the extent possible. The conductive member has a conductive support and a conductive layer, the conductive layer contains a rubber composition formed of a modified epichlorohydrin rubber, and the modified epichlorohydrin rubber has a unit represented by the following formula (1). In the formula (1), R1, R2, and R3 each independently represent hydrogen or a saturated hydrocarbon group having 1 to 18 carbon atoms.
    Type: Application
    Filed: October 2, 2017
    Publication date: February 8, 2018
    Inventors: Norifumi Muranaka, Satoru Yamada, Kazuhiro Yamauchi, Seiji Tsuru, Yuka Muranaka
  • Patent number: 9853031
    Abstract: A semiconductor device includes an active region on a substrate, a device isolation film on the substrate to define the active region, a gate trench including a first portion in the active region and a second portion in the device isolation film, a gate electrode including a first gate embedded in the first portion of the gate trench and a second gate embedded in the second portion of the gate trench, a first gate capping pattern on the first gate and filling the first portion of the gate trench, and a second gate capping pattern on the second gate and filling the second portion of the gate trench, an upper surface of the first gate being higher than an upper surface of the second gate, and the first gate capping pattern and the second gate capping pattern have different structures.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: December 26, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Hee Cho, Woo Song Ahn, Min Su Choi, Satoru Yamada, Jun Soo Kim, Sung Sam Lee
  • Patent number: 9811021
    Abstract: Provided is such a conductive member that a change in its electrical resistance value caused by its long-term use is reduced to the extent possible. The conductive member has a conductive support and a conductive layer, the conductive layer contains a rubber composition formed of a modified epichlorohydrin rubber, and the modified epichlorohydrin rubber has a unit represented by the following formula (1). In the formula (1), R1, R2, and R3 each independently represent hydrogen or a saturated hydrocarbon group having 1 to 18 carbon atoms.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: November 7, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Norifumi Muranaka, Satoru Yamada, Kazuhiro Yamauchi, Seiji Tsuru, Yuka Muranaka
  • Publication number: 20170257683
    Abstract: An apparatus, system, and method of remotely monitoring receives, from an operation terminal, identification information and location information of a location of one or more lamps, stores, in a memory, the received identification information and the received location information in association with each other for the one or more lamps, updates log information regarding a log of a lighting condition of the one or more lamps, in response to an indication that an electric circuit of the one or more lamps is energized for the one or more lamps, and sends monitoring information corresponding to the log information of the electric circuit of the one or more lamps for display.
    Type: Application
    Filed: March 2, 2017
    Publication date: September 7, 2017
    Inventor: SATORU YAMADA
  • Publication number: 20170243973
    Abstract: A semiconductor device including a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and an insulating layer covering an inner sidewall of the trench, wherein the inner sidewall of the trench has at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes.
    Type: Application
    Filed: December 28, 2016
    Publication date: August 24, 2017
    Inventors: Sungsam LEE, Junsoo KIM, Hyoshin AHN, Satoru YAMADA, Joohyun JEON, MoonYoung JEONG, Chunhyung CHUNG, Min Hee CHO, Kyo-Suk CHAE, Eunae CHOI
  • Publication number: 20170221623
    Abstract: An electronic component includes; a magnetic-body core having a plate-shaped portion and a core portion which extends from an upper surface of the plate-shaped portion; a winding wire which includes a wound portion wound by a rectangular wire into an Edgewise winding form and two non-wound portions extending from the wound portion to two distal ends, and the core portion is inserted through the wound portion; and a magnetic exterior body which covers at least the wound portion and the core portion. The two non-wound portions are respectively arranged along a bottom surface and at least one of the side surfaces of the plate-shaped portion. Parts of the two non-wound portions arranged along the bottom surface are electrodes.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Inventors: Mitsugu KAWARAI, Satoru YAMADA, Kazuyuki KIKUCHI, Tomohiro KAJIYAMA, Juichi OOKI, Motomi TAKAHASHI, Tsutomu OTSUKA