Abstract: A packaging and filling device, a paper container, and a blank is disclosed, in which the container is substantially protected from permeation leakage from an end surface. The blank for the paper container comprises an upper part, a bottom part, and a cylindrical main body having four side walls and a square cross-section, and is formed by a packaging and filling device. The packaging and filling device comprises a loading unit for retrieving the blank and loading a cylindrical blank, a bottom-part-molding unit for molding the bottom part of the cylindrical blank and obtaining a container, a filling unit for filling the container with a liquid food item from an upper opening, and an upper-part-sealing unit for heat-sealing the upper opening.

Abstract: A packaging and filling device, a paper container, and a blank is disclosed. The blank comprises a sixth panel in a readily foldable state prior to a step for forming a bottom part, and provides sufficient length in a folded portion to protect the end surface of a packaging material. The blank for the paper container is formed by the packaging and filling device and comprises a top part, a bottom part, and a cylindrical body having four side walls and a square cross-section. The packaging and filling device comprises a loading unit for retrieving the blank and loading a cylindrical blank, a bottom-part-molding unit for molding the bottom part of the cylindrical blank to obtain a container, a filling unit for filling the container with liquid food from an upper opening, and an upper-part-sealing unit for heat-sealing the upper opening.

Abstract: A packaging and filling device, a paper container, and a blank is disclosed. The blank comprises a sixth panel in a readily foldable state prior to a step for forming a bottom part, and provides sufficient length in a folded portion to protect the end surface of a packaging material. The blank for the paper container is formed by the packaging and filling device and comprises a top part, a bottom part, and a cylindrical body having four side walls and a square cross-section. The packaging and filling device comprises a loading unit for retrieving the blank and loading a cylindrical blank, a bottom-part-molding unit for molding the bottom part of the cylindrical blank to obtain a container, a filling unit for filling the container with liquid food from an upper opening, and an upper-part-sealing unit for heat-sealing the upper opening.

Abstract: A packaging and filling device, a paper container, and a blank is disclosed, in which the container is substantially protected from permeation leakage from an end surface. The blank for the paper container comprises an upper part, a bottom part, and a cylindrical main body having four side walls and a square cross-section, and is formed by a packaging and filling device. The packaging and filling device comprises a loading unit for retrieving the blank and loading a cylindrical blank, a bottom-part-molding unit for molding the bottom part of the cylindrical blank and obtaining a container, a filling unit for filling the container with a liquid food item from an upper opening, and an upper-part-sealing unit for heat-sealing the upper opening.

Abstract: A circuit for auto-focus adjustment includes a calculating unit configured to calculate an indicator of randomness of pixel values in a captured image, a direction determining unit configured to compare a first value of the indicator calculated by the calculating unit in a preceding focus adjustment process with a second value of the indicator calculated by the calculating unit after the calculation of the first value, thereby to determine a direction of focus shift in response to a result of the comparison, and a control unit configured to start a focus adjustment process by which a focus position is first moved in the direction of focus shift determined by the direction determining unit.

Abstract: Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1, an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

Abstract: A circuit for auto-focus adjustment includes a calculating unit configured to calculate an indicator of randomness of pixel values in a captured image, a direction determining unit configured to compare a first value of the indicator calculated by the calculating unit in a preceding focus adjustment process with a second value of the indicator calculated by the calculating unit after the calculation of the first value, thereby to determine a direction of focus shift in response to a result of the comparison, and a control unit configured to start a focus adjustment process by which a focus position is first moved in the direction of focus shift determined by the direction determining unit.

Abstract: An interface conversion macro converts a signal compliant with a system interface specification output from a controller to a signal compliant with a memory interface specification, and outputs the same to a memory interface part, and it also converts a signal output from the memory macro to a signal compliant with the system interface specification and outputs the same to the controller. By converting the system interface specification and the memory interface specification to each other by an interface conversion macro, a common memory macro can be mounted on a semiconductor integrated circuit even when the system interface specification differs. Accordingly, when designing a system, the design verification time, evaluation time, and test time of the semiconductor integrated circuit can be reduced. As a result, the design time and design cost of the semiconductor integrated circuit can be reduced.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: A memory controller connected to memory includes: an address reception unit for receiving an address code externally input together with a command; and a command conversion unit for outputting to the memory an MRS command to change the internal settings of the memory based on the address code when the address code input together with a first command specifies an address space for which the memory is not implemented.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: A semiconductor device, including a word line driver for driving a word line connected to a memory cell in a memory cell array and for resetting the word line when the memory cell changes from an activated to a standby state. The reset level of the word line driver is set when resetting of the word line is performed, and may be switched between first and second potentials. A word line reset level generating circuit varies the amount of negative potential current supply in accordance with memory cell array operating conditions. The semiconductor device includes a plurality of power source circuits, each having an oscillation circuit and a capacitor, for driving the capacitor via an oscillation signal outputted by the oscillation circuit. At least some power source circuits share a common oscillation circuit, and different capacitors are driven via the common oscillation signal.

Abstract: A dynamic semiconductor memory has a plurality of memory blocks and a memory core. Each of the memory blocks has a sense amplifier, and the memory core is formed from memory cells located at intersections between a plurality of word lines and a plurality of bit lines connected to the sense amplifier. The memory blocks are sequentially refreshed by selecting each of the word lines and by simultaneously activating the memory cells connected to the selected word line by the sense amplifier. The dynamic semiconductor memory has a first refresh counter which outputs a first internal refresh candidate address, and a second refresh counter which outputs a second internal refresh candidate address that is different from the first internal refresh candidate address. When an externally accessed address coincides with the first internal refresh candidate address, a refresh operation is performed starting from the second internal refresh candidate address.

Abstract: A semiconductor memory for inputting and outputting data synchronously with a clock includes a clock reception unit for receiving the clock, and a command reception unit for initially receiving a first specific command synchronizing with the clock after turning a power on, after a low-power standby or after an initialization, followed by starting a command reception.

Abstract: Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1, an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

Abstract: Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

Abstract: An interface conversion macro converts a signal compliant with a system interface specification output from a controller to a signal compliant with a memory interface specification, and outputs the same to a memory interface part, and it also converts a signal output from the memory macro to a signal compliant with the system interface specification and outputs the same to the controller. By converting the system interface specification and the memory interface specification to each other by an interface conversion macro, a common memory macro can be mounted on a semiconductor integrated circuit even when the system interface specification differs. Accordingly, when designing a system, the design verification time, evaluation time, and test time of the semiconductor integrated circuit can be reduced. As a result, the design time and design cost of the semiconductor integrated circuit can be reduced.

Abstract: A twin-cell type semiconductor memory device in which the area of a chip can be reduced. In the twin-cell type semiconductor memory device for storing data in at least one pair of memory cells as complementary information, memory cells are arranged at each of a plurality of word lines at intervals at which bit lines are located. At least the one pair of memory cells, which have stored the complementary information and which indicate a plurality of areas each connected to a pair of bit lines, form a twin cell.

Abstract: A semiconductor memory device includes a memory configured to input/output first data and second data in parallel, the first data being all or part of a predetermined number of bits, and the second data being comprised of a number of bits necessary to correct error of the predetermined number of bits, a unit configured to supply redundancy switching information in response to an address signal supplied to the memory, and a controlling unit situated between the memory and input/output nodes, having a first path that couples a given bit of the input/output nodes to a corresponding bit of the first data of the memory and a second path that couples the given bit of the input/output nodes to a predetermined bit of the second data of the memory, and configured to select and enable one of the first path and the second path in response to the redundancy switching information.

Abstract: A delay circuit includes a delay part delaying a signal by a delay time which can be varied based on a control current, and a control current adjustment circuit adjusting the control current so that the delay time changes linearly based on a variation in a resistance value.