Patents by Inventor Satoshi Eto

Satoshi Eto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6549154
    Abstract: A digital-to-analog converter circuit includes a converter configured to convert digital signals of bit n (n=0, 1, 2, . . . , N) to voltage values, a plurality of amplifiers configured to output currents having different values in accordance with the voltage values, and an adder configured to assigning weights to the currents and adding the currents together in response to the digital signal of bit n.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: April 15, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Isobe, Satoshi Eto
  • Publication number: 20030065997
    Abstract: A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern(s) for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern(s) outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern(s) (the first test mode) generated within the logic chip or the external test pattern (the second test mode) supplied from the exterior.
    Type: Application
    Filed: April 16, 2002
    Publication date: April 3, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Masafumi Yamazaki, Takaaki Suzuki, Toshikazu Nakamura, Satoshi Eto, Toshiya Miyo, Ayako Sato, Takayuki Yoneda, Noriko Kawamura
  • Publication number: 20030058007
    Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.
    Type: Application
    Filed: October 23, 2002
    Publication date: March 27, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Masao Taguchi, Satoshi Eto, Yoshihiro Takemae, Hiroshi Yoshioka, Makoto Koga
  • Publication number: 20030058008
    Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.
    Type: Application
    Filed: October 23, 2002
    Publication date: March 27, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Masao Taguchi, Satoshi Eto, Yoshihiro Takemae, Hiroshi Yoshioka, Makoto Koga
  • Publication number: 20030048690
    Abstract: A semiconductor device includes input circuits which capture respective data pieces from an exterior of the device in synchronization with respective clock signals supplied from the exterior of the device, a pulse signal generation circuit which generates a pulse signal, and drive circuits which supplies the respective data pieces captured by the input circuits to internal circuitry at a unified timing corresponding to the pulse signal.
    Type: Application
    Filed: March 13, 2002
    Publication date: March 13, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Akira Kikutake, Satoshi Eto
  • Publication number: 20030042944
    Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.
    Type: Application
    Filed: October 23, 2002
    Publication date: March 6, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Masao Taguchi, Satoshi Eto, Yoshihiro Takemae, Hiroshi Yoshioka, Makoto Koga
  • Patent number: 6512717
    Abstract: A semiconductor memory device includes a core area formed of memory blocks each having a relaxed sense amplifier arrangement, a data bus including data bus lines corresponding to the memory blocks, a plurality of input/output terminals provided in number corresponding to the data bus lines forming the data bus, and a data path switch circuit provided between the data bus the input/output terminals for providing interconnection paths between the input/output terminals and the data bus lines, wherein the data path switch circuit switches a part of the interconnection paths in response to a switch control signal such that the input/output terminals are connected respectively to predetermined memory cells located at respective, predetermined physical locations in any of the memory blocks.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: January 28, 2003
    Assignee: Fujitsu Limited
    Inventors: Satoshi Eto, Masato Matsumiya, Shusaku Yamaguchi, Toshikazu Nakamura, Hideki Kano, Ayako Kitamoto, Mitsuhiro Higashiho
  • Patent number: 6492846
    Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By this constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: December 10, 2002
    Assignee: Fujitsu Limited
    Inventors: Masao Taguchi, Satoshi Eto, Yoshihiro Takemae, Hiroshi Yoshioka, Makoto Koga
  • Publication number: 20020145447
    Abstract: A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.
    Type: Application
    Filed: October 5, 1999
    Publication date: October 10, 2002
    Inventors: AYAKO KITAMOTO, MASATO MATSUMIYA, SATOSHI ETO, MASATO TAKITA, TOSHIKAZU NAKAMURA, HIDEKI KANOU, KUNINORI KAWABATA, MASATOMO HASEGAWA, TORU KOGA, YUKI ISHII
  • Publication number: 20020140459
    Abstract: A semiconductor integrated circuit device comprises a plurality of MIS transistors, and an integrated circuit unit including logic gate circuits configured by a combination of the plurality of MIS transistors. Each of the MIS transistors has a gate including a circuit element represented by an equivalent circuit in which a capacitance and resistance are parallel-connected.
    Type: Application
    Filed: March 25, 2002
    Publication date: October 3, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Haruki Toda, Kenji Tsuchida, Satoshi Eto, Kuninori Kawabata
  • Publication number: 20020125928
    Abstract: A digital-to-analog converter circuit includes a converter configured to convert digital signals of bit n (n=0, 1, 2, . . . , N) to voltage values, a plurality of amplifiers configured to output currents having different values in accordance with the voltage values, and an adder configured to assigning weights to the currents and adding the currents together in response to the digital signal of bit n.
    Type: Application
    Filed: December 10, 2001
    Publication date: September 12, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Isobe, Satoshi Eto
  • Publication number: 20020054525
    Abstract: A semiconductor memory device includes a core area formed of memory blocks each having a relaxed sense amplifier arrangement, a data bus including data bus lines corresponding to the memory blocks, a plurality of input/output terminals provided in number corresponding to the data bus lines forming the data bus, and a data path switch circuit provided between the data bus the input/output terminals for providing interconnection paths between the input/output terminals and the data bus lines, wherein the data path switch circuit switches a part of the interconnection paths in response to a switch control signal such that the input/output terminals are connected respectively to predetermined memory cells located at respective, predetermined physical locations in any of the memory blocks.
    Type: Application
    Filed: July 29, 1996
    Publication date: May 9, 2002
    Inventors: SATOSHI ETO, MASATO MATSUMIYA, SHUSAKU YAMAGUCHI, TOSHIKAZU NAKAMURA, HIDEKI KANO, AYAKO KITAMOTO, MITSUHIRO HIGASHIHO
  • Patent number: 6384671
    Abstract: An electronic circuit apparatus having a bus, a plurality of stubs branched from the bus, and a plurality of semiconductor devices having signal input/output terminals connected to the corresponding stubs. The electronic circuit apparatus includes at least one impedance circuit arranged between the bus and at least one of the stubs, and each impedance circuit has a high-pass filter characteristic. Therefore, ringing is suppressed, attenuation in the high-frequency components of a transmission signal is prevented, the definition of the signal is maintained, and transmission frequency and speed are both improved.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: May 7, 2002
    Assignee: Fujitsu Limited
    Inventors: Masao Taguchi, Satoshi Eto, Yoshinori Okajima
  • Patent number: 6377101
    Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: April 23, 2002
    Assignee: Fujitsu Limited
    Inventors: Satoshi Eto, Masao Taguchi, Masato Matsumiya, Toshikazu Nakamura, Masato Takita, Mitsuhiro Higashiho, Toru Koga, Hideki Kano, Ayako Kitamoto, Kuninori Kawabata, Koichi Nishimura, Yoshinori Okajima
  • Publication number: 20020027430
    Abstract: A clock synchronizing method is provided. The clock synchronizing method comprises the step of detecting a phase difference of a synchronous clock from a reference clock, and the step of varying a phase of the synchronous clock in one direction when the phase difference is not within a predetermined range, and varying the phase of the synchronous clock in one of the one direction and the other direction according to the phase difference when the phase difference is within the predetermined range.
    Type: Application
    Filed: August 15, 2001
    Publication date: March 7, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Satoshi Eto
  • Publication number: 20020021157
    Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.
    Type: Application
    Filed: February 22, 2000
    Publication date: February 21, 2002
    Inventors: Satoshi Eto, Masao Taguchi, Masato Matsumiya, Toshikazu Nakamura, Masato Takita, Mitsuhiro Higashiho, Toru Koga, Hideki Kano, Ayako Kitamoto, Kuninori Kawabata, Koichi Nishimura, Yoshinori Okajima
  • Patent number: 6339345
    Abstract: In an output circuit 10, a latch circuit 11, a phase difference controlled circuit 12 and an output buffer circuit 13 are cascaded and a DATA is clocked into the latch circuit 11. A replica circuit 20 is a down-scaled version of a layout pattern of the output circuit 10, comprises circuits 21 to 23 corresponding to the circuits 11, 12 and 13, and a CLK is provided through a delay circuit 5 and a divide-by-2 frequency divider 16 to the data input of the latch circuit 21 as a data. The output of the replica circuit 20 is provided through a dummy load circuit 24 and a low pass filter 25 to a comparator 26, the output thereof is compared with a reference voltage Vref to generate count-up or count-down pulses. The pulses are counted by an up-down counter 27 whose count is provided to the phase difference controlled circuit 12 and its replica 22 to reduce the phase difference between rising and falling edges of the output signal of the output buffer circuit 23.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: January 15, 2002
    Assignees: Fujitsu Limited, Kabushiki Kaisha Toshiba
    Inventors: Satoshi Eto, Hironobu Akita, Katsuaki Isobe
  • Patent number: 6337834
    Abstract: The present invention provides a synchronous signal generation circuit that can be operated with a high accuracy, at a high speed and with a low power consumption without being affected by the process dispersion. The synchronous signal generation circuit of the present invention comprises a real circuit including an input receiver, an off-chip driver, and a mirror-type synchronous circuit, and a dummy circuit for determining the delay time in the mirror-type synchronous circuit, the dummy circuit including an input receiver and an off-chip driver. In the dummy circuit, the input signal is supplied first to the off-chip driver and, then, to the input receiver so as to permit the signal between the off-chip driver and the input receiver to be a small amplitude signal. It follows that the real circuit and the dummy circuit are equal to each other in the signal levels in the input and output portions of each of the input receiver and the off-chip driver.
    Type: Grant
    Filed: November 7, 2000
    Date of Patent: January 8, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Isobe, Hironobu Akita, Satoshi Eto, Haruki Toda
  • Patent number: 6333658
    Abstract: An analog synchronization circuit includes an input buffer which is supplied with an external clock signal, a delay monitor which is supplied with a clock signal output from the input buffer, an output buffer for outputting a clock signal synchronous with the external clock signal and two charge balance delay circuits. The two charge balance delay circuits are equivalent to delay lines in a mirror type delay locked loop. Each charge balance delay circuits operates once in two consecutive cycles of the external clock signal. The two charge balance delay circuits alternately operate and output signals of the charge balance delay circuits are supplied to the output buffer via an OR gate. First and second capacitors are provided in each charge balance delay circuits. A first current source circuit charges the first capacitor for a time equivalent to a delay time of a forward pulse. The second capacitor is charged by a second current source circuit.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: December 25, 2001
    Assignees: Kabushiki Kaisha Toshiba, Fujitsu Limited
    Inventors: Hironobu Akita, Satoshi Eto, Katsuaki Isobe, Masaharu Wada, Haruki Toda
  • Patent number: 6313674
    Abstract: A variable delay line outputs a clock signal advanced in phase by a time corresponding to a sum tH+tL of a time tH required to output high level data from an OCD circuit and a time tL required to output low level data from the OCD circuit. A replica circuit for outputting low level data has the same configuration as a circuit portion of the OCD circuit through which low level data passes. The replica circuit outputs a start signal SSH for outputting high level data from the OCD circuit. Another replica circuit for outputting high level data has the same configuration as a circuit portion of the OCD circuit through which high level data passes. The replica circuit outputs a start signal SSL for outputting low level data from the OCD circuit.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: November 6, 2001
    Assignees: Kabushiki Kaisha Toshiba, Fujitsu Limited
    Inventors: Hironobu Akita, Satoshi Eto, Katsuaki Isobe