Abstract: A variable delay line outputs a clock signal advanced in phase by a time corresponding to a sum tH+tL of a time tH required to output high level data from an OCD circuit and a time tL required to output low level data from the OCD circuit. A replica circuit for outputting low level data has the same configuration as a circuit portion of the OCD circuit through which low level data passes. The replica circuit outputs a start signal SSH for outputting high level data from the OCD circuit. Another replica circuit for outputting high level data has the same configuration as a circuit portion of the OCD circuit through which high level data passes. The replica circuit outputs a start signal SSL for outputting low level data from the OCD circuit.

Abstract: According to a semiconductor memory for one aspect of the present invention, a memory cell transistor is formed in a P-type first well region which is formed at the surface of a P-type semiconductor substrate, and a back bias voltage is applied to the P-type first well region and the P-type substrate. Further, an N-type retrograde region is formed by implanting a high energy N-type impurity, so that a deeper, N-type second well region is formed by employing the N-type retrograde region. Further, a P-type third well region is formed in the N-type second well region, and a P-type emitter region is also formed therein. Thus, together the P-type emitter region, the N-type second well region, and the P-type third well region constitute a lateral PNP transistor. In addition, the ground voltage is maintained for the P-type third well region, which serves as a collector region.

Abstract: A semiconductor device having the function of generating an internal clock signal delayed by a predetermined phase by adjusting the phase of an external clock signal, includes a first clock phase circuit for roughly adjusting the phase of the external clock signal; and a second clock phase adjusting circuit for controlling the phase of the internal clock signal with higher accuracy than the first clock phase adjusting circuit. The semiconductor device having such a construction executes phase comparisons by the first and second clock phase adjusting circuits independently of each other, and when a phase control operation by the second clock phase adjusting circuit is made subordinate to that of the first clock phase adjusting circuit, the delay time of each of a plurality of delay elements inside the first clock phase adjusting circuit is set to a value larger than a power source jitter resulting from a noise of a power source and a jitter of the external clock signal.

Abstract: It is one aspect of the present invention to split a common data bus established in common for a plurality of segments into a read-dedicated common data bus and a write dedicated common data bus, in a memory device comprising a plurality of segments each of which includes a plurality of memory cells. With such a constitution, write data can be supplied to the write data bus even when read data are present on the read common data bus due to a read operation; and even when operation frequencies increase, there are no limitations to the timing of write operations following reading and the speed of write operations following reading can be increased.

Abstract: A semiconductor memory device has data bus lines which are connected to a memory cell array, and column selection lines, each of which is used to select a column of the memory cell array. The semiconductor memory device includes a shielding line placed between the column selection line and a data bus line adjacent to the column selection line. The shielding line electrically shields the data bus line from the column selection line. Therefore, the semiconductor memory device having the high speed data bus can be achieved because the coupling capacitance between the column selection line and the data bus line is reduced.

Abstract: A semiconductor integrated circuit producing a given output voltage includes first and second operational amplifiers, and first and second transistors. The first and second operational amplifiers detect a voltage difference between a voltage applied to an input terminal and at least one reference voltage. The first and second transistors are turned ON or turned OFF according to the levels of voltages output from the first and second operational amplifiers. The first operational amplifier receives the output voltage at the input terminal. When the level of the output voltage becomes lower than the reference voltage, the first operational amplifier allows the first transistor to operate so as to raise the output voltage. In contrast, the second operational amplifier receives the output voltage at the input terminal. When the level of the output voltage exceeds the reference voltage, the second operational amplifier allows the second transistor to operate so as to lower the output voltage.

Abstract: A semiconductor memory device includes a memory cell array having a number of memory cells configured in a square or rectangular formation, the memory cell array having predetermined capacitive loads which are different at different memory locations, the capacitive loads including a smallest capacitive load and a largest capacitive load. A refresh address counter outputs a number of bit signals which constitute a refresh address signal, the refresh address signal indicating an address of a memory cell to be refreshed in the memory device, the bit signals having predetermined high/low-state change periods which are different from each other, the bit signals including a first bit signal corresponding to the smallest capacitive load and a second bit signal corresponding to the largest capacitive load.

Abstract: For cutting off a path for flowing a read detection current from a high-potential power supply (Vii) of a read data bus amplifier (S/B 33) to the ground side of a read controller (41) via a sense amplifier (31) selected based on an address in a write to a memory cell, a semiconductor memory device have a logic circuit (42, 43) for calculating logic between a block select signal and a write status signal to change the potential at the read controller (41) to the same power supply potential as that at the S/B (33) when the write status signal is activated. This logic circuit can prevent any unwanted read detection current from flowing in a data write, so as to suppress current consumption in a write.

Abstract: A semiconductor device has a DLL circuit or the like for adjusting the phase of an external clock and producing an internal clock that lags behind by a given phase. The semiconductor device further includes a clock frequency judging unit for judging the frequency of a first clock on the basis of an indication signal indicating a delay value of the first clock in the DLL circuit or the like to output a control signal; and a clock selecting unit for selecting either one of the first clock and the second clock, in response to the control signal.

Abstract: In the present invention, the gate electrodes of the bit line transfer gates for bit line pair selection that perform connection and isolation of the sense amplifiers and bit line pairs are put into floating condition during activation of the sense amplifier in the active period. Thus, a system is adopted according to which the potential of the bit line is driven to power source voltage Vcc or high voltage corresponding thereto by the sense amplifier in the active condition, the pre-charging potential of the bit line pair being made lower than half the power source voltage Vcc, for example ground potential Vss.

Abstract: A clock supplying circuit that supplies a clock to a plurality of controlled circuits 451-454 arranged in respectively different positions. A forward and backward wiring 41, 42 and an internal clock supply wiring 43 are arranged along controlled circuits. A main clock drive circuit 40 is for outputting a first clock to the forward wiring 41 and is for outputting a second shorter phase than the first clock to the internal clock supply wiring 43. A plurality of local clock drive circuits 441-444 arranged close to the controlled circuits, are supplied with a forward clock propagated along the forward wiring and with a back clock propagated along the backward wiring, and are also supplied with the second clock, for delaying the phase of the supplied second clock so as to coincide with a phase intermediate the forward clock and the back clock, and for supplying the delayed clock of the second clock to the respectively corresponding controlled circuits as local clock.

Abstract: A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks.

Abstract: A phase comparator is adapted to output a predetermined number of pulse signals corresponding to the phase difference between a comparison reference signal and a comparison object signal to be compared therewith. This phase comparator is applied to a DLL (Delay Locked Loop) circuit having a delay circuit, a dummy delay circuit and a delay controller. Further, the phase comparator has a phase comparing section and a pulse number control section. The phase comparing section is used to make a judgement by comparing the phase difference between the comparison reference signal and the comparison object signal with a predetermined value, and the pulse number control section is used to control a number of pulses to be output according to a result of the judgement made by the phase comparing section.

Abstract: In a semiconductor integrated circuit having the function of executing a pre-charge operation of a data bus when data is transferred to the data bus from a plurality of driver circuits connected to the data bus, a reset circuit for executing the pre-charge operation of the data bus is constituted so as to start the pre-charge operation of the data bus upon receiving an end timing of a strobe signal. Preferably, the reset circuit detects that the data bus reaches a pre-charge level for executing the pre-charge operation, and then terminates the pre-charge operation. On the other hand, in a semiconductor integrated circuit having a data latch function by a pipeline system when the data is read out from a memory cell, etc.

Abstract: In a data bus amplifier activation method for a semiconductor memory device having a memory cell array, a column selection circuit for selecting a column in the memory cell array, a read data bus for transferring read data, output from the column selected by the column selection circuit, to a read data bus amplifier, and a write data bus for transferring write data, output from a write data bus amplifier, to the column selected by the column selection circuit, the read data bus amplifier or the write data bus amplifier is activated by detecting the selection of the column effected by the column selection circuit.

Abstract: The present invention relates to a memory device including memory cells each formed of a cell transistor connected to bit and word line and a cell capacitor. The memory device includes a pre-charging circuit for pre-charging bit line to a first voltage, a sense amplifier for detecting voltages of bit lines and driving the bit lines to a second voltage for H level or a third voltage for L level, and a word line driving circuit for driving word lines to make the writing voltage for H level of the cell capacitor to a fourth voltage lower than the second voltage. The present invention is characterized in that the first voltage is lower than an intermediate value between the second and third voltages. According to the present invention, it becomes possible to prevent the voltage V.sub.

Abstract: A semiconductor memory device includes a memory cell connected to a bit line and a word line, a bit line precharge circuit which precharges the bit line to a ground voltage, and a word decoder which sets the word line to a negative voltage when the word line is not selected.

Abstract: This invention is a memory device with a structure that has eliminated the logic circuit using I/O mask signal DQM from within the critical path from the clock CLK to the predecoder and column decoder for generating column selection signal CL. The logic circuit using I/O mask signal DQM within the critical path for generating column selection signals is eliminated, and the time from when the clock is supplied until the column selection signal is generated is made as short as possible. On the other hand, to make an I/O mask possible during burst write mode, drive control of the write amplifier is performed based on I/O mask signal DQM. Specifically, activation of the write amplifier is prohibited or allowed in response to the I/O mask signal DQM.

Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

Abstract: A semiconductor device which operates in synchronism with a first clock externally provided. The semiconductor device includes a clock-generation circuit generating a second clock which maintains a predetermined phase relation with the first clock, a check circuit for checking a frequency of the first clock based on at least one internal signal generated by the clock-generation circuit, and an internal circuit which switches an operation mode according to results of the checking.