Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: A semiconductor memory device includes word drivers for selectively activating word lines with respect to memory cells. The semiconductor memory device further includes a control unit for controlling a gate voltage of transistors in the word drivers so as to reduce inter-band tunnel currents of the transistors.

Abstract: An electronic circuit apparatus having a bus, a plurality of stubs branched from the bus, and a plurality of semiconductor devices having signal input/output terminals connected to the corresponding stubs. The electronic circuit apparatus includes at least one impedance circuit arranged between the bus and at least one of the stubs, and each impedance circuit has a high-pass filter characteristic. Therefore, ringing is suppressed, attenuation in the high-frequency components of a transmission signal is prevented, the definition of the signal is maintained, and transmission frequency and speed are both improved.

Abstract: A semiconductor memory device includes at least one cell block including an array of memory cells, a plurality of sense amplifiers which temporarily hold data of the memory cells, a first data bus connected to the plurality of sense amplifiers via first gates, and a second data bus having a direct electrical connection to the first data bus and being laid out to extend through a position of the at least one cell block.

Abstract: An electronic device includes a first circuit which refers to an external clock and thus produces a first internal clock, and a second circuit which refers to the first internal clock and thus produces a second internal clock. The first circuit has a first phase error between the external clock and the first internal clock, and the second circuit has a second phase error between the first internal clock and the second internal clock. The first phase error has a sign reverse to that of the second phase error.

Abstract: An nMOS transistor 31 has a gate connected to a bit line *BL with its source and drain short-circuited and connected to a dummy word line DWL0. After setting the bit lines BL and *BL to a precharge potential Vpr=Vii/2, a transfer gate 11 is turned on. Next, the potential on the dummy word line DWL0 is raised from Vs=Vpr-Vth, where Vth is a threshold voltage of the nMOS 31, to Vii and then a sense amplifier 30 is set in an active state. If a pMOS transistor is employed in place of the nMOS transistor 31, its source and drain are short-circuited and connected to the bit line *BL with its gate connected to the dummy word line DWL0.

Abstract: An output buffer circuit includes a portion for receiving an input signal in which a level thereof is changed from a high level to a low level and vice versa, and a circuit block for operating based on the input signal received by the portion and for outputting an output signal in which a level thereof is changed from a high level to a low level and vice versa in response to level transition of the input signal, the circuit block including a circuit arrangement of a plurality of FETs for temporarily lowering an output resistance of the circuit block in level transition of the output signal.

Abstract: A semiconductor memory controls the timing of refreshing memory cells. The semiconductor memory has a capacitor for holding charges, a precharge circuit, and a current source. The precharge circuit has at least a transistor for precharging the capacitor. The current source has a positive temperature coefficient to increase a current as the temperature rises and discharges the capacitor. The timing of refreshing the memory cells is controlled according to a temporal change in the voltage of the capacitor. This arrangement is capable of refreshing the memory cells in a refresh period adjusted to the actual data hold time of the memory cells.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of this input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.