Patents by Inventor Satoshi Ishibashi

Satoshi Ishibashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4486768
    Abstract: A gate controlled semiconductor device is provided having a main electrode member consisting of a cathode electrode assembly formed in one end layer of a wafer of semiconductive material and an anode electrode assembly formed in other end layer of said wafer, a main thyristor portion, an auxiliary thyristor portion and a bias controlling member. Said main thyristor portion is constructed by at least one control electrode assembly which is provided in the vicinity of the cathode electrode assembly of the main electrode member. Said auxiliary thyristor portion includes an additional layer which is provided on the one layer of the wafer and being adjacent to the cathode electrode assembly and the auxiliary thyristor portion is forcedly switched on and off by said bias controlling member.
    Type: Grant
    Filed: August 26, 1983
    Date of Patent: December 4, 1984
    Assignee: Kabushiki Kaisha Meidensha
    Inventors: Tetsuro Sueoka, Satoshi Ishibashi
  • Patent number: 4433340
    Abstract: Disclosed is an optical recording medium. This optical recording medium has a substrate made of a transparent material such as an acrylic resin; and a recording layer for receiving an energy beam such as a laser beam whose intensity is changed in response to quantized information and for receiving desired information by melt-deforming in response to the intensity of the energy beam. The recording layer contains tellurium as a base material and carbon at a predetermined content of 40 atomic percent.
    Type: Grant
    Filed: March 22, 1982
    Date of Patent: February 21, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Masao Mashita, Nobuaki Yasuda, Tomoyuki Ishibshi, deceased, Satoshi Ishibashi, legal representative
  • Patent number: 4291325
    Abstract: A gate controlled semiconductor device comprises two main electrode members provided on a wafer having at least one junction formed between two alternately different conductivity typed semiconductive layers and a control electrode member in which the same or a different conductivity typed surface is provided on one layer of the wafer. The control electrode member is provided on the wafer adjacent one of the main electrodes. The control electrode member includes a low resistance layer embedded in one surface of the wafer and consists of a wide bridging portion, a plurality of relatively wide main trunk portions projecting from the bridging portion and a plurality of narrow branch portions branching from the main trunk portions.
    Type: Grant
    Filed: January 4, 1980
    Date of Patent: September 22, 1981
    Assignee: Kabushiki Kaisha Meidensha
    Inventors: Tetsuro Sueoka, Satoshi Ishibashi
  • Patent number: 4092703
    Abstract: A gate controlled semiconductor device in which a gate electrode is substantially divided into many pieces. The semiconductor device comprises a semiconductive element having at least one P-N junction formed by at least a pair of P-type diffusion regions and N-type diffusion regions, a plurality of cathode assemblies including a metallic layer deposited on a cathode-emitter layer formed on a surface of said semiconductive element, an anode electrode assembly and gate electrode assemblies. The latter includes a plurality of separated metallic layers provided around the cathode electrode assemblies of the cathode-emitter layer. The cathode electrode assemblies are of a radial and spiral shape and the divided gate electrode assemblies have also a ring shape and/or circular shape.
    Type: Grant
    Filed: March 15, 1977
    Date of Patent: May 30, 1978
    Assignee: Kabushiki Kaisha Meidensha
    Inventors: Tetsuro Sueoka, Satoshi Ishibashi