Patents by Inventor Satoshi Maeda

Satoshi Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5324612
    Abstract: A toner for electrophotography which comprises, as a binder resin, a polyester resin obtained from carboxylic acids containing aromatic monomer in a proportion of 80 mol % or more relative to the entire carboxylic acid component, and alcohols containing aliphatic diols having 2 to 4 carbon atoms in a proportion of 70-100 mol % relative to the entire alcohol component and alicyclic alcohols in a proportion of 0-30 mol % relative to the entire alcohol component, and having a specific gravity of 1.3 or more, a glass transition temperature of 58.degree. C. or more, and a number average molecular weight of 1,000-6,000. The toner of the present invention is superior in image characteristics, fixability, storage stability (resistance to blocking), resistance to plasticizer and charge stability.
    Type: Grant
    Filed: August 18, 1992
    Date of Patent: June 28, 1994
    Assignee: Toyo Boseki Kabushiki Kaisha
    Inventors: Satoshi Maeda, Yasunari Hotta, Minako Arichi, Yohzo Yamada, Tetsuo Shimomura, Yoshihiro Ikuzawa
  • Patent number: 5295004
    Abstract: An optical beam scanning apparatus includes one rotatable hologram which is rotatable about an axis, and at least two laser beam sources which emit laser beams. The rotatable hologram is provided with at least two hologram areas whose number corresponds to the number of the laser beam sources, so that the laser beams emitted from the respective laser beam sources are made incident upon the respective hologram areas. Each of the hologram areas is provided with a plurality of hologram facets which are concentrically arranged with respect to the axis of rotation of the rotatable hologram to emit laser beams of the same F number. The hologram areas having different numbers of hologram facets having different F numbers.
    Type: Grant
    Filed: November 6, 1992
    Date of Patent: March 15, 1994
    Assignee: Fujitsu Limited
    Inventors: Shinya Hasegawa, Fumio Yamagishi, Youji Houki, Shigetake Iwata, Shigeo Kayashima, Satoshi Maeda
  • Patent number: 5293336
    Abstract: A semiconductor memory device has a memory cell composed of a select MOS transistor and information storage capacitor and a peripheral circuit composed of a MOS transistor formed at a peripheral side of the memory cell, these transistors being formed in the surface portion of a first conductivity type semiconductor substrate. In the semiconductor memory device, the gate oxide film of the select MOS transistor is different in thickness from the gate oxide film of the MOS transistor of the peripheral circuit, the gate electrodes of these transistors being simultaneously formed.
    Type: Grant
    Filed: October 29, 1991
    Date of Patent: March 8, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeaki Ishii, Satoshi Maeda
  • Patent number: 5237478
    Abstract: A rotary head drum unit for a recording/reproducing apparatus comprises a stationary upper drum provided at its lower end with a taper surface for biasing a magnetic tape downward, a stationary lower drum provided in its circumference with a helical tape lead or guide surface to guide the lower edge of a tape helically extended across the upper and lower drums, and rotary heads inserted between the upper and lower drums. At least a portion of the taper surface of the upper drum in a lead-out region near a position where the magnetic tape departs from the rotary head drum unit is a helical taper section extended helical substantially in parallel to the helical tape lead or guide surface of the lower drum.
    Type: Grant
    Filed: July 9, 1991
    Date of Patent: August 17, 1993
    Assignee: Sony Corporation
    Inventors: Jun Sawai, Hiroshi Kiriyama, Keisuke Hashimoto, Satoshi Maeda
  • Patent number: 5224082
    Abstract: A method for detecting a tracking error in a process of tracking a groove track on a recording medium includes the steps of: irradiating a first light spot onto a groove track on a recording medium as a focused light beam for carrying out recording, reproducing, or erasing of information on the groove track of the recording medium; and irradiating a second and a third light spots onto an area around the groove track on the recording medium as focused light beams simultaneously with the irradiation of the first light spot, the second and third light spots are irradiated onto an area around the groove track on one side of the first light spot in a manner such that each of the second and third light spots covers both an inside and outside of the groove track.
    Type: Grant
    Filed: February 6, 1992
    Date of Patent: June 29, 1993
    Assignee: Fujitsu Limited
    Inventors: Kaneyuki Kurokawa, Masayuki Kato, Satoshi Maeda, Fumio Yamagishi, Hiroyuki Ikeda
  • Patent number: 5110766
    Abstract: A method of manufacturing a semiconductor device, in particular a contact portion of the wiring of the device. An insulating layer is formed on a semiconductor substrate, a contact hole is formed on the insulating layer by etching, and a first conductive layer having hollows is formed on the insulating layer and in the contact hole. Next, a flattening layer is formed to flatten the surface of device structure, and a part of the first conductive layer is exposed by etching the flattening layer to permit a part of the flattening layer to remain in hollows of device structure. Next, a second conductive layer is formed on the remaining flattening layer and the exposed part of the first conductive layer, and is connected to the semiconductor substrate.
    Type: Grant
    Filed: July 6, 1990
    Date of Patent: May 5, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Maeda, Shizuo Sawada, Satoshi Shinozaki
  • Patent number: 5079183
    Abstract: Element separate regions consisting of insulation material are provided on a semiconductor substrate of a first conductivity type. Element regions which respectively consist of monocrystalline semiconductor layers of the first and second conductivity types are provided in at least two adjacent regions among a plurality of island substrate regions separated by the element separate regions. An impurity layer is provided in that portion between the substrate and at least one of the element regions.
    Type: Grant
    Filed: January 6, 1989
    Date of Patent: January 7, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Maeda, Hiroshi Iwai
  • Patent number: 5004704
    Abstract: A Phospho Silicate Glass layer is used for an insulation layer between a lower wiring layer including a refractory metal silicide and an upper wiring layer in a semiconductor device of a multilevel interconnection structure. A reflow treatment is performed on the Phospho Silicate Glass layer using steam. A part of the lower wiring layer is oxidized during the reflow treatment, and the resistivity of the lower wiring layer is simultaneously lowered during the reflow treatment.
    Type: Grant
    Filed: October 30, 1989
    Date of Patent: April 2, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Maeda, Shizuo Sawada
  • Patent number: 4922864
    Abstract: An improved system for controlling air intake for an engine of a vehicle. Each curved intake manifold includes high speed intake passages having a larger diameter and a shorter length and low speed intake passages having a smaller diameter and a longer distance. Valves are disposed between a chamber and the high speed intake passages on the both banks. To open or close the valves in dependency on the engine speed, an actuator including a negative pressure chamber is installed on the chamber. The actuator is controlled by a crank angle sensor detecting the engine speed.
    Type: Grant
    Filed: July 12, 1989
    Date of Patent: May 8, 1990
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventor: Satoshi Maeda
  • Patent number: 4888208
    Abstract: There is provided a method of producing a ceramic substrate for printed circuits wherein at least the surface of the side to be circuit-printed is subjected to a roughening treatment with one of the following compounds:(1) substances containing sulfur trioxide and(2) substances which, upon decomposition, generate sulfur trioxide.
    Type: Grant
    Filed: October 1, 1987
    Date of Patent: December 19, 1989
    Assignee: Toyo Boseki Kabushiki Kaisha
    Inventors: Satoshi Maeda, Ryu Yoneda, Kenichi Yokota, Hideo Miyake
  • Patent number: 4872042
    Abstract: In a semiconductor device, a MOS transistor is formed in an island-like semiconductor region formed in a semiconductor substrate. The switching of the MOS transistor is controlled by changing a potential in the semiconductor region by means of a control circuit.
    Type: Grant
    Filed: July 13, 1984
    Date of Patent: October 3, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Maeda, Hiroshi Iwai
  • Patent number: 4833647
    Abstract: The semiconductor memory device of the present invention is formed on an integrated substrate and is immune to alpha radiation. The device includes a semiconductor substrate of a first conductive type and a memory cell formed in the substrate which has a switching MOS transistor having at least a first impurity region of a second conductive type and a capacitor connected to the transistor for storing memory data. A second impurity region of the first conductive type and having a higher concentration than that of the substrate is provided on the substrate surface at a position covering the first impurity region.
    Type: Grant
    Filed: September 5, 1986
    Date of Patent: May 23, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Maeda, Shizuo Sawada
  • Patent number: 4832464
    Abstract: An optical system having a grating lens assembly including a first grating lens which diffracts rays of a beam incident thereupon so as to provide non-parallel diffraction rays and a second grating lens which converges the non-parallel diffraction rays at a predetermined point substantially without aberration.
    Type: Grant
    Filed: September 18, 1987
    Date of Patent: May 23, 1989
    Assignee: Fujitsu Limited
    Inventors: Masayuki Kato, Satoshi Maeda, Fumio Yamagishi, Hiroyuki Ikeda, Takefumi Inagaki
  • Patent number: 4827886
    Abstract: A pulse generator disk is secured to a crankshaft of an engine. The disk has notches representing a compression top dead center of each cylinder. A first magnetic pickup is provided for producing a first output signal in accordance with the notches. A rotary member is secured to a camshaft of the engine. The member has toothed portions comprising projections provided at positions corresponding to respective cylinders. The number of the projections in each toothed portion is set to represent a corresponding cylinder. A second magnetic pickup is provided for producing a second output signal in accordance with the projections. A control system is provided to respond to the second output signal determining the number of the projections to produce a cylinder designating signal, and to respond to the first output signal after the cylinder designating signal to produce a crank angle signal.
    Type: Grant
    Filed: December 14, 1987
    Date of Patent: May 9, 1989
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventor: Satoshi Maeda
  • Patent number: 4794563
    Abstract: This invention provides a semiconductor memory device for an integrated circuit comprising a semiconductor substrate of a first conductivity type, a field insulation layer on the semiconductor substrate, and a switch. This switch includes a gate insulation layer, a gate electrode on the gate insulation layer, and a pair of impurity regions of a second conductivity type in the substrate adjacent to the gate electrode. The device also includes a capacitor including a first electrode connected to one impurity region, a second electrode connected to a predetermined voltage, insulation means for separating the first and second electrodes, and groove means extending into the substrate for increasing the capacitace area of the first electrode.A method for making the devices is also described.
    Type: Grant
    Filed: October 31, 1986
    Date of Patent: December 27, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Maeda
  • Patent number: 4787355
    Abstract: A pulse generator disk is secured to a crankshaft of an engine. The disk has notches representing a compression top dead center of each cylinder. A first magnetic pickup is provided for producing a first output signal in accordance with the notch. A rotary member is secured to a camshaft of the engine. The rotary member has projections provided at positions corresponding to respective cylinders. A second magnetic pickup is provided for producing a second output signal in accordance with the projections. A control system is provided to respond to the first output signal to produce a crank angle signal. When the first output signal does not generate at a proper timing, a crank angle signal is produced dependent on the second output signal.
    Type: Grant
    Filed: February 5, 1988
    Date of Patent: November 29, 1988
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventor: Satoshi Maeda
  • Patent number: 4768467
    Abstract: A valve mechanism for an intake valve has a cam block including a first cam comprising a base circle and a second cam having a lobe and a base circle the diameter of which is equal to that of the base circle of the first cam. A first rocker arm engaging with the first cam and a second rocker arm engaging with the second cam are provided. The first and second rocker arms are rotatably engaged with each other so as to be independently rocked by corresponding cams, and have holes in which a lock pin engages to connect the first and second rocker arms with each other so as to be rocked together by the second cam. The system is arranged to engage and disengage the pin with and from both the holes of the first and second rocker arms at a time when both the rocker arms engage with the base circles at the same time.
    Type: Grant
    Filed: January 16, 1987
    Date of Patent: September 6, 1988
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventors: Takemasa Yamada, Hajime Kashiwase, Satoshi Maeda
  • Patent number: 4755863
    Abstract: A high-performance, high-integration, and a highly reliable semiconductor device has a semiconductor substrate, an element isolation layer of an insulating material which is formed on the semiconductor substrate, a monocrystalline semiconductor layer formed on the portion of the semiconductor substrate and isolated from the element isolation layer, and a semiconductor element formed in the monocrystalline semiconductor layer. The impurity concentration of at least the surface region of the semiconductor substrate which is covered with the element isolation layer is not less than 10.sup.16 /cm.sup.3.
    Type: Grant
    Filed: August 15, 1986
    Date of Patent: July 5, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Maeda, Hiroshi Iwai
  • Patent number: 4730588
    Abstract: A system is provided for an automotive engine comprising two intake valves for one cylinder, and a camshaft having cams for operating the intake valves. One of the cams is rotatably and axially slidably mounted on the camshaft. An eccentric conical hole is in a side of the cam and an eccentric conical portion is formed on the camshaft. A hydraulic cylinder is formed between the cam and the camshaft to form an oil chamber so as to shift the cam, and a spring is provided for urging the cam to the oil chamber. When the cam is shifted by the operation of the cylinder, the eccentric conical hole of the cam is engaged with the conical portion at a predetermined angular position.
    Type: Grant
    Filed: April 20, 1987
    Date of Patent: March 15, 1988
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventor: Satoshi Maeda
  • Patent number: 4642878
    Abstract: A method for manufacturing a semiconductor device is disclosed which comprises the steps of forming an element isolating region of a first conductivity type, forming an insulating film on the surface of the element region which is isolated by the element isolating region, selectively forming a gate electrode on the insulating film, doping an impurity of a second conductivity type into the element region as a first doping step with the gate electrode and element isolating region as masks; sequentially forming a oxidizable first film and a second film on the whole surface of the resultant structure, anisotropically etching the second film to partly leave the second film area on that portion of the oxidizable first film which is located on the side wall of the gate electrode, doping an impurity of a second conductivity type with the remaining second film, gate electrode and element isolating region as masks, removing the remaining second film, and converting the oxidizable first film to an oxide film.
    Type: Grant
    Filed: August 28, 1985
    Date of Patent: February 17, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Maeda