Patents by Inventor Satoshi Shimizu

Satoshi Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10923498
    Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory openings are formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer. A memory film is formally formed by a conformal deposition process, and a source contact layer is formed in the source cavity. Vertical semiconductor channels and drain regions are formed in remaining volumes of the memory openings on sidewalls of the source contact layer. A backside contact via structure is formed through the alternating stack and directly on a sidewall of the source contact layer.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 16, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yoshitaka Otsu, Satoshi Shimizu, Makoto Koto
  • Publication number: 20210036004
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film including a silicon nitride layer and a tunneling dielectric layer is formed in the memory opening, and an opening is formed through the memory film. A chemical oxide layer is formed on a physically exposed surface of an underlying semiconductor material portion. A silicon nitride ring can be formed by selectively growing a silicon nitride material from an annular silicon nitride layer portion of the silicon nitride layer while suppressing deposition of the silicon nitride material on the tunneling dielectric layer and on the chemical oxide layer. A vertical semiconductor channel can be formed by depositing a continuous semiconductor material layer on the underlying semiconductor material portion and the tunneling dielectric layer and on the silicon nitride ring.
    Type: Application
    Filed: September 26, 2019
    Publication date: February 4, 2021
    Inventors: Takumi MORIYAMA, Yasushi DOWAKI, Yuki KASAI, Satoshi SHIMIZU, Jayavel PACHAMUTHU
  • Publication number: 20210024963
    Abstract: Provided is a method for producing an organic substance from a syngas by microbial fermentation, wherein only the solid component can be efficiently separated from an organic substance-containing liquid obtained by microbial fermentation to reduce the content of microorganisms, etc. Disclosed is a method for producing an organic substance from a syngas containing carbon monoxide by microbial fermentation, which comprises a microbial fermentation step wherein the syngas is fed to a microbial fermenting vessel and a liquid containing an organic substance is obtained by microbial fermentation, a solid-liquid separation step wherein the organic substance-containing liquid is separated into a solid component containing microorganisms and a liquid component containing an organic substance, and an extraction step wherein the organic substance-containing liquid is extracted from the liquid component, wherein the organic substance-containing liquid is heated to 40° C.
    Type: Application
    Filed: March 3, 2019
    Publication date: January 28, 2021
    Applicant: SEKISUI CHEMICAL CO., LTD.
    Inventors: Satoshi SHIMIZU, Kohoro HAMACHI, Kazuto NATSUYAMA, Kanetomo SATO
  • Patent number: 10879260
    Abstract: A bonded assembly includes a first memory die containing a first three-dimensional memory device, a second memory die containing a second three-dimensional memory device, and a support die bonded to the first memory die and comprising a peripheral circuitry configured to control the first three-dimensional memory device and the second three-dimensional memory device. The first memory die includes multiple rows of first-die proximal bonding pads, multiple rows of first-die distal bonding pads, and a plurality of first-die laterally-shifting electrically conductive paths connecting a respective one of the first-die proximal bonding pads and a respective one of the first-die distal bonding pads that is laterally offset from the respective one of the first-die proximal bonding pads. The first memory die and the second memory die can have an identical layout, and electrical connections can be shifted through the first memory die by the offset distance.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: December 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tatsuya Uryu, Satoshi Shimizu, Nobuyuki Fujimura
  • Publication number: 20200397954
    Abstract: The purpose of the present invention is to provide an anti-adhesion material having a high anti-adhesion effect. The present invention pertains to an anti-adhesion material comprising a biocompatible sponge-like layered body having a sponge-like first layer and a sponge-like second layer both being at least partially crosslinked with a curing agent and comprising a low endotoxin monovalent metal salt of alginic acid. The monovalent metal salt of alginic acid in the first layer has a weight average molecular weight of 30000 to 300000. The monovalent metal salt of alginic acid in the second layer has a weight average molecular weight of 1000 to 200000. The weight average molecular weights are determined by GPC-MALS after a de-crosslinking treatment. The weight average molecular weight of the monovalent metal salt of alginic acid in the first layer is higher than the weight average molecular weight of the monovalent metal salt of alginic acid in the second layer.
    Type: Application
    Filed: January 15, 2018
    Publication date: December 24, 2020
    Applicants: Mochida Pharmaceutical Co., Ltd., The University of Tokyo
    Inventors: Taichi ITO, Seiichi OHTA, Kiyoshi HASEGAWA, Mitsuko ISAJI, Satoshi SHIMIZU, Daichi TANAKA
  • Patent number: 10854627
    Abstract: In-process source-level material layers including a source-level sacrificial layer are formed over a substrate, and an alternating stack of insulating layers and spacer material layers and memory stack structures are formed over the in-process source-level layers. A backside trench is formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer employing an etchant provided through the backside trench. A source contact layer including a doped semiconductor material is formed on vertical semiconductor channels of the memory stack structures within the source cavity. The source contact layer includes an unfilled cavity, which is subsequently filled with a silicon nitride liner, a silicon oxide fill material and a semiconductor cap. A semiconductor oxide structure can be formed by filling voids in the silicon oxide fill material by oxidizing the semiconductor cap into a thermal semiconductor oxide material portion.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 1, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takumi Moriyama, Satoshi Shimizu, Kiyohiko Sakakibara
  • Publication number: 20200374261
    Abstract: [Problem] An ENUM/DNS system with enhanced processing efficiency is provided. [Solution] Provided is an ENUM/DNS system 100 including an ENUM/DNS client 20 that performs a connection destination information query indicating a connection destination associated with a telephone number of a destination terminal added to a connection request transmitted from an originating terminal, and an ENUM/DNS server 10 that receives the connection destination information query and outputting the connection destination as a connection destination information query response. The ENUM/DNS server 10 includes a determination unit configured to determine an attribute of the originating terminal based on the connection destination information query, and a conversion unit configured to convert a SIP domain included in REGEXP of the connection destination information query response to a SIP domain indicating the connection destination based on the attribute.
    Type: Application
    Filed: February 18, 2019
    Publication date: November 26, 2020
    Inventors: Yuki HANAZAWA, Satoshi SHIMIZU, Shiro AOSHIMA
  • Publication number: 20200343258
    Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory openings are formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer. A memory film is formally formed by a conformal deposition process, and a source contact layer is formed in the source cavity. Vertical semiconductor channels and drain regions are formed in remaining volumes of the memory openings on sidewalls of the source contact layer. A backside contact via structure is formed through the alternating stack and directly on a sidewall of the source contact layer.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Inventors: Yoshitaka OTSU, Satoshi SHIMIZU, Makoto KOTO
  • Publication number: 20200320696
    Abstract: A medical image processing apparatus includes: a display unit; and circuitry configured to: acquire volume data including tissues, and set a first mask region and a second mask region which include a voxel to be rendered among a plurality of voxels included in the volume data; set a first plane which intersects both the first mask region and the second mask region; display a first image in which a first region formed by cutting the first mask region by the first plane and the second mask region are rendered; receive through an operation unit a first operation for setting a second plane which is parallel to the first plane and intersects both the first mask region and the second mask region; and display a second image in which a second region formed by cutting the first mask region by the second plane and the second mask region are rendered.
    Type: Application
    Filed: April 3, 2020
    Publication date: October 8, 2020
    Inventors: Shusuke CHINO, Tsuyoshi NAGATA, Satoshi SHIMIZU, Yasuhiro KONDO, Yutaka KARASAWA, Shinichiro SEO
  • Publication number: 20200289547
    Abstract: The present invention provides a composition for filling the nucleus pulposus of an intervertebral disc, the composition containing a low endotoxin monovalent metal salt of alginic acid. The composition is applied to a nucleus pulposus site of a subject, is used so as to be cured partially after application, and has fluidity when applied to the nucleus pulposus site. Accordingly, a composition for filling nucleus pulposus is provided, the composition being capable of promoting the regeneration of the nucleus pulposus of an intervertebral disc.
    Type: Application
    Filed: January 27, 2017
    Publication date: September 17, 2020
    Applicants: National University Corporation Hokkaido University, Mochida Pharmaceutical Co., Ltd
    Inventors: Hideki SUDO, Takeru TSUJIMOTO, Norimasa IWASAKI, Satoshi SHIMIZU, Mitsuko ISAJI
  • Publication number: 20200286815
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. At least one dielectric material portion is formed over the substrate adjacent to the alternating stack. Memory stack structures are formed through the alternating stack. A trench extending through the alternating stack and a via cavity extending through the at least one dielectric material portion are formed using a same anisotropic etch process. The via cavity is deeper than the trench and the via cavity extends into an upper portion of the substrate. The sacrificial material layers are replaced with electrically conductive layers using the trench as a conduit for an etchant and a reactant. A trench fill structure is formed in the trench, and a via structure assembly is formed in the via cavity using simultaneous deposition of material portions. A bonding pad may be formed on the bottom surface of the via structure assembly.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Inventors: Takumi Moriyama, Hiroshi Sasaki, Yohei Masamori, Satoshi Shimizu
  • Publication number: 20200279861
    Abstract: A bonded assembly includes a first memory die containing a first three-dimensional memory device, a second memory die containing a second three-dimensional memory device, and a support die bonded to the first memory die and comprising a peripheral circuitry configured to control the first three-dimensional memory device and the second three-dimensional memory device. The first memory die includes multiple rows of first-die proximal bonding pads, multiple rows of first-die distal bonding pads, and a plurality of first-die laterally-shifting electrically conductive paths connecting a respective one of the first-die proximal bonding pads and a respective one of the first-die distal bonding pads that is laterally offset from the respective one of the first-die proximal bonding pads. The first memory die and the second memory die can have an identical layout, and electrical connections can be shifted through the first memory die by the offset distance.
    Type: Application
    Filed: February 28, 2019
    Publication date: September 3, 2020
    Inventors: Tatsuya Uryu, Satoshi Shimizu, Nobuyuki Fujimura
  • Publication number: 20200237755
    Abstract: The present invention provides a heterocyclic compound represented by the general formula (1): The compound of the present invention has a wide treatment spectrum for mental disorders including central nervous system disorders, no side effects and high safety.
    Type: Application
    Filed: April 14, 2020
    Publication date: July 30, 2020
    Applicant: Otsuka Pharmaceutical Co., Ltd.
    Inventors: Hiroshi YAMASHITA, Nobuaki ITO, Shin MIYAMURA, Kunio OSHIMA, Jun MATSUBARA, Hideaki KURODA, Haruka TAKAHASHI, Satoshi SHIMIZU, Tatsuyoshi TANAKA
  • Patent number: 10720445
    Abstract: A lower source-level semiconductor layer, a sacrificial semiconductor layer, an upper source-level semiconductor layer, and an alternating stack of insulating layers and sacrificial material layers are sequentially formed over a substrate. An array of memory stack structures containing vertical semiconductor channels that extend through the alternating stack and into an upper portion of the lower source-level semiconductor layer is formed. A backside trench is formed through the alternating stack, and a source cavity is formed by removing the sacrificial semiconductor layer. A doped source contact layer is formed on each of the vertical semiconductor channels in the source cavity. A silicon nitride liner is formed on the doped source contact layer. The sacrificial material layers are replaced with electrically conductive layers. A dielectric wall structure is formed in the backside trench.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Satoshi Shimizu, Takumi Moriyama, Kiyohiko Sakakibara
  • Publication number: 20200188736
    Abstract: A scoring method executed by a processor, includes: acquiring sensor data obtained by measuring a competitor in a scoring competition; extracting joint information of the competitor, based on an analysis result of the sensor data; acquiring an evaluation item and an evaluation index that correspond to the joint information of the competitor, based on a rule in which a posture specified by a series of joint motions and joint angles, the evaluation item, and the evaluation index for performance evaluation are associated with each other; and evaluating a success or failure of a skill and a degree of perfection of the skill in a performance of the competitor, based on the analysis result, the evaluation item, and the evaluation index.
    Type: Application
    Filed: February 27, 2020
    Publication date: June 18, 2020
    Applicant: FUJITSU LIMITED
    Inventors: HIROHISA NAITO, Tsuyoshi MATSUMOTO, Satoshi SHIMIZU, Akihiko Yabuki, HIDEAKI HIRANO
  • Publication number: 20200179759
    Abstract: A display method executed by a processor includes: acquiring a recognition result of a plurality of elements included in a series of exercise that have been recognized based on 3D sensing data for which the series of exercise by a competitor in a scoring competition is sensed and element dictionary data in which characteristics of elements in the scoring competition are defined; identifying, based on the recognition result of the elements, a displayed element in a 3D model video corresponding to the series of exercise based on the 3D sensing data; determining a part of options to be a subject of display, in accordance with the displayed element, out of a plurality of options corresponding to a plurality of evaluation indexes concerning scoring of the scoring competition; and displaying the part of options in a mode to be selectable.
    Type: Application
    Filed: November 19, 2019
    Publication date: June 11, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Kazumi Kubota, HIROHISA NAITO, Satoshi SHIMIZU
  • Patent number: D884741
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: May 19, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Kazuhiro Arima, Tomohiro Takizawa, Satoshi Shimizu, Kazumi Kubota, Hirohisa Naito, Tsuyoshi Matsumoto
  • Patent number: RE48059
    Abstract: The present invention provides a heterocyclic compound represented by the general formula (1): The compound of the present invention has a wide treatment spectrum for mental disorders including central nervous system disorders, no side effects and high safety.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: June 23, 2020
    Assignee: Otsuka Pharmaceutical Co., Ltd.
    Inventors: Hiroshi Yamashita, Nobuaki Ito, Shin Miyamura, Kunio Oshima, Jun Matsubara, Hideaki Kuroda, Haruka Takahashi, Satoshi Shimizu, Tatsuyoshi Tanaka, Yasuo Oshiro, Shinichi Taira
  • Patent number: D892863
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: August 11, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Kazuhiro Arima, Tomohiro Takizawa, Satoshi Shimizu, Kazumi Kubota, Hirohisa Naito, Tsuyoshi Matsumoto
  • Patent number: D910539
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: February 16, 2021
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masayuki Nakano, Satoshi Shimizu, Tomohisa Yoshie, Atsushi Fukui, Masato Sasaki, Yuki Watanabe, Daisuke Toyoshima