Patents by Inventor Satoshi Torii

Satoshi Torii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220387971
    Abstract: [Problem] In an embodiment involving addition of a chelating agent in an upstream process of the process for production, such as the polymerization step, the residual ratio of the chelating agent in the final product, a particulate water-absorbing agent, is improved. [Solution] A particulate water-absorbing agent having a poly(meth)acrylic acid (salt)-based water-absorbing resin as a main component, containing a chelating agent having a nitrogen atom and an inorganic reducing agent having a sulfur atom, wherein the particulate water-absorbing agent has a chelating agent ratio of 0.8 to 1.
    Type: Application
    Filed: November 12, 2020
    Publication date: December 8, 2022
    Inventors: Satoshi MATSUMOTO, Kanako TSURU, Taishi KOBAYASHI, Daisuke TAKAGI, Kazushi TORII
  • Patent number: 11414998
    Abstract: A turbine blade includes an airfoil portion having a hollow portion extending along the blade height direction and film cooling holes arranged along the blade height direction, and an insert disposed in the hollow portion along the blade height direction and having impingement cooling holes. The insert includes a first high-density opening region having a higher density of the impingement cooling holes than in other surface regions of the insert. The geometric center of the first high-density opening region is positioned on the suction side of the airfoil portion in the leading-edge-to-trailing-edge direction and on the outer side of the midpoint of the airfoil portion in the blade height direction. The film cooling holes includes upstream film cooling holes disposed in the suction surface of the airfoil portion at a position corresponding to the first high-density opening region or at a position closer to a leading edge than the position.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: August 16, 2022
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Takashi Fujii, Hidemichi Koyabu, Shunsuke Torii, Satoshi Hada
  • Patent number: 11384643
    Abstract: A turbine blade, a gas turbine, an intermediate product of the turbine blade, and a method of manufacturing the turbine blade are disclosed. The turbine blade has a blade body having hollow shape, cavities defined inside the blade body, and a cooling passage that opens from the cavities to a rear end portion of the blade body. The cooling passage includes: a first passage on a third cavity side and having a width that becomes narrower from the third cavity side toward the rear end portion of the blade body; and a second passage on a rear end portion side of the blade body and having a width that is constant from the third cavity side toward the rear end portion of the blade body.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: July 12, 2022
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Yoshimasa Takaoka, Shunsuke Torii, Hidemichi Koyabu, Saki Matsuo, Yasuoki Tomita, Satoshi Hada, Yoshifumi Okajima
  • Patent number: 10818356
    Abstract: A nonvolatile semiconductor memory device includes a selection transistor and a memory transistor that are formed on a well for each of a plurality of memory cells. At a time of a data read from the memory transistor, a first voltage is applied to the well and a source of the memory transistor, and a second voltage is applied to a gate of the selection transistor included in a non-selected memory cell among the plurality of memory cells. The first voltage is smaller than an absolute value of the second voltage.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 27, 2020
    Assignee: UNITED SEMICONDUCTOR JAPAN CO., LTD.
    Inventors: Satoshi Torii, Shu Ishihara
  • Publication number: 20190333580
    Abstract: A nonvolatile semiconductor memory device includes a selection transistor and a memory transistor that are formed on a well for each of a plurality of memory cells. At a time of a data read from the memory transistor, a first voltage is applied to the well and a source of the memory transistor, and a second voltage is applied to a gate of the selection transistor included in a non-selected memory cell among the plurality of memory cells. The first voltage is smaller than an absolute value of the second voltage.
    Type: Application
    Filed: January 31, 2019
    Publication date: October 31, 2019
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Satoshi Torii, Shu Ishihara
  • Patent number: 10249637
    Abstract: A manufacturing method of a semiconductor device includes: forming a tunnel oxide layer and a charge-storage layer in a region of a flash memory transistor; forming a first oxide film; removing the first oxide film in regions of a first transistor and a second transistor; forming a third oxide film by adding a first oxide layer between a first oxide film and a semiconductor substrate in a region of a third transistor while forming a second oxide film in the regions of the first transistor and the second transistor by oxidation; removing the second oxide film in the region of the first transistor; and forming a fifth oxide film by adding a second oxide layer between the second oxide film and the semiconductor substrate in the region of the second transistor while forming a fourth oxide film in the region of the first transistor by oxidation, and forming a sixth oxide film by adding a third oxide layer between the first oxide layer and the semiconductor substrate in the region of the third transistor.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: April 2, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Satoshi Torii, Hideaki Matsumura, Shu Ishihara
  • Publication number: 20180261617
    Abstract: A manufacturing method of a semiconductor device includes: forming a tunnel oxide layer and a charge-storage layer in a region of a flash memory transistor; forming a first oxide film; removing the first oxide film in regions of a first transistor and a second transistor; forming a third oxide film by adding a first oxide layer between a first oxide film and a semiconductor substrate in a region of a third transistor while forming a second oxide film in the regions of the first transistor and the second transistor by oxidation; removing the second oxide film in the region of the first transistor; and forming a fifth oxide film by adding a second oxide layer between the second oxide film and the semiconductor substrate in the region of the second transistor while forming a fourth oxide film in the region of the first transistor by oxidation, and forming a sixth oxide film by adding a third oxide layer between the first oxide layer and the semiconductor substrate in the region of the third transistor.
    Type: Application
    Filed: February 22, 2018
    Publication date: September 13, 2018
    Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Satoshi Torii, Hideaki Matsumura, Shu Ishihara
  • Patent number: 9704592
    Abstract: A semiconductor storage device including plural bit lines, plural select gate lines that intersect with the plural bit lines, and plural memory cells that each include a p-channel memory transistor. The semiconductor storage device includes plural p-channel charging transistors that are respectively connected to the plural bit lines, and a charging line that is connected to each of the plurality of charging transistors. A controller that ON/OFF controls the charging transistors places each of the charging transistors in an ON state prior to read current flowing in a read target bit line, and that places the charging transistor connected to the read target bit line in an OFF state when read current flows in the read target bit line.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: July 11, 2017
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Satoshi Torii
  • Publication number: 20170040064
    Abstract: A semiconductor storage device including plural bit lines, plural select gate lines that intersect with the plural bit lines, and plural memory cells that each include a p-channel memory transistor. The semiconductor storage device includes plural p-channel charging transistors that are respectively connected to the plural bit lines, and a charging line that is connected to each of the plurality of charging transistors. A controller that ON/OFF controls the charging transistors places each of the charging transistors in an ON state prior to read current flowing in a read target bit line, and that places the charging transistor connected to the read target bit line in an OFF state when read current flows in the read target bit line.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 9, 2017
    Inventor: Satoshi Torii
  • Publication number: 20160240543
    Abstract: A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.
    Type: Application
    Filed: April 21, 2016
    Publication date: August 18, 2016
    Inventors: Satoshi Torii, Hideaki Matsumura, Hikaru Kokura, Etsuro Kawaguchi, Katsuaki Ookoshi, Yuka Kase, Kengo Inoue
  • Patent number: 9349600
    Abstract: A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: May 24, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Satoshi Torii, Hideaki Matsumura, Hikaru Kokura, Etsuro Kawaguchi, Katsuaki Ookoshi, Yuka Kase, Kengo Inoue
  • Patent number: 9287277
    Abstract: A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: March 15, 2016
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Tatsuya Sugimachi, Satoshi Torii
  • Patent number: 9224745
    Abstract: A method of manufacturing a semiconductor device includes: forming a conductive film on a semiconductor substrate; patterning the conductive film in a memory region to form a first gate electrode; after forming the first gate electrode, forming a mask film above each of the conductive film in a logic region and the first gate electrode; removing the mask film in the logic region; forming a first resist film above the mask film left in the memory region and above the conductive film left in the logic region; and forming a second gate electrode in the logic region by etching the conductive film using the first resist film as a mask.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: December 29, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Satoshi Torii
  • Publication number: 20150137211
    Abstract: A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 21, 2015
    Inventors: Satoshi TORII, Hideaki MATSUMURA, Hikaru KOKURA, Etsuro KAWAGUCHI, Katsuaki OOKOSHI, Yuka KASE, Kengo INOUE
  • Patent number: 8897079
    Abstract: Local bit lines (LBL) are respectively provided for a plurality of sectors, corresponding to each of the global bit lines (GBL). Sector select transistors connect a LBL to a GBLector select lines control the on/off state of the sector select transistors for the corresponding sectors. A plurality of word lines (WL) intersect the local bit lines. Memory cells are located at the intersections between the LBL and the WL. Each memory cell connects a source line with the corresponding LBL and includes an n-channel transistor that is turned on/off by the corresponding WL. A precharge voltage is applied to a charging line. Charging transistors connect the LBL to the charging line. A charging gate line controls the on/off state of the charging transistors.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: November 25, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Satoshi Torii
  • Patent number: 8649226
    Abstract: A nonvolatile semiconductor memory device including a first bit line commonly coupling drain sides memory cells; a word line commonly coupling control gates of memory cell transistors; a column decoder coupled to a second bit line; a row decoder coupled to a word line; a first transistor having a source coupled to the first bit line and having a drain electrically coupled to the column decoder via the second bit line; and a first control unit for controlling potential of a gate of the first transistor, the memory cell transistor being formed over a first well, the first transistor being formed over a second well electrically isolated from the first well, a film thickness of a gate insulation film of the first transistor being smaller than that of a gate insulation film of a second transistor formed in the row decoder and coupled to the word line.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: February 11, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Satoshi Torii
  • Patent number: 8604533
    Abstract: A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: December 10, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tatsuya Sugimachi, Satoshi Torii
  • Patent number: 8507971
    Abstract: The present invention provides an apparatus and method for a non-volatile memory comprising at least one array of memory cells with shallow trench isolation (STI) regions between bit lines for increased process margins. Specifically, in one embodiment, each of the memory cells in the array of memory cells includes a source, a control gate, and a drain, and is capable of storing at least one bit. The array of memory cells further includes word lines that are coupled to control gates of memory cells. The word lines are arranged in rows in the array. In addition, the array comprises bit lines coupled to source and drains of memory cells. The bit lines are arranged in columns in the array. Also, the array comprises at least one row of bit line contacts for providing electrical conductivity to the bit lines. Further, the array comprises shallow trench isolation (STI) regions separating each of the bit lines along the row of bit line contacts.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: August 13, 2013
    Assignee: Spansion LLC
    Inventor: Satoshi Torii
  • Patent number: 8503234
    Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: August 6, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi
  • Patent number: 8400828
    Abstract: A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: March 19, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Satoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi