Patents by Inventor Satyarth Suri

Satyarth Suri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190189913
    Abstract: The present disclosure relates to the fabrication of spin transfer torque memory devices, wherein a magnetic tunnel junction of the spin transfer torque memory device is formed with Heusler alloys as the fixed and free magnetic layers and a tunnel barrier layer disposed between and abutting the fixed Heusler magnetic layer and the free Heusler magnetic layer, wherein the tunnel barrier layer is lattice matched to the free Heusler magnetic layer. In one embodiment, the tunnel barrier layer may be a strontium titanate layer.
    Type: Application
    Filed: September 27, 2016
    Publication date: June 20, 2019
    Applicant: Intel Corporation
    Inventors: Brian Doyle, Kaan Oguz, Satyarth Suri, Kevin O'Brien, Mark Doczy, Charles Kuo
  • Publication number: 20190109281
    Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF).
    Type: Application
    Filed: December 10, 2018
    Publication date: April 11, 2019
    Applicant: INTEL CORPORATION
    Inventors: BRIAN S. DOYLE, KAAN OGUZ, CHARLES C. KUO, MARK L. DOCZY, SATYARTH SURI, DAVID L. KENCKE, ROBERT S. CHAU, ROKSANA GOLIZADEH MOJARAD
  • Publication number: 20190035677
    Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.
    Type: Application
    Filed: March 30, 2016
    Publication date: January 31, 2019
    Inventors: Manish CHANDHOK, Richard E. SCHENKER, Hui Jae YOO, Kevin L. LIN, Jasmeet S. CHAWLA, Stephanie A. BOJARSKI, Satyarth SURI, Colin T. CARVER, Sudipto NASKAR
  • Publication number: 20190027537
    Abstract: Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of dielectric layer above a substrates, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.
    Type: Application
    Filed: March 28, 2016
    Publication date: January 24, 2019
    Inventors: Christopher J. WIEGAND, Oleg GOLONZKA, MD Tofizur RAHMAN, Brian S. DOYLE, Mark L. DOCZY, Kevin P. O'BRIEN, Kaan OGUZ, Tahir GHANI, Satyarth SURI
  • Patent number: 10158065
    Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF).
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: December 18, 2018
    Assignee: INTEL CORPORATION
    Inventors: Brian S. Doyle, Kaan Oguz, Charles C. Kuo, Mark L. Doczy, Satyarth Suri, David L. Kencke, Robert S. Chau, Roksana Golizadeh Mojarad
  • Publication number: 20180323367
    Abstract: An embodiment includes an apparatus comprising: first and second electrodes on a substrate; a perpendicular magnetic tunnel junction (pMTJ), between the first and second electrodes, comprising a dielectric layer between a fixed layer and a free layer; and an additional dielectric layer directly contacting first and second metal layers; wherein (a) the first metal layer includes an active metal and the second metal includes an inert metal, and (b) the second metal layer directly contacts the free layer. Other embodiments are described herein.
    Type: Application
    Filed: June 26, 2015
    Publication date: November 8, 2018
    Inventors: Brian S. Doyle, Kaan Oguz, Kevin P. O'Brien, David L. Kencke, Elijah V. Karpov, Charles C. Kuo, Mark L. Doczy, Satyarth Suri, Robert S. Chau, Niloy Mukherjee, Prashant Majhi
  • Publication number: 20180248116
    Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for removing a re-deposited layer and/or interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.
    Type: Application
    Filed: September 18, 2015
    Publication date: August 30, 2018
    Applicant: Intel Corporation
    Inventors: Mark L. DOCZY, Brian S. DOYLE, Charles C. KUO, Kaan OGUZ, Kevin P. O'BRIEN, Satyarth SURI, Tejaswi K. INDUKURI
  • Publication number: 20180240969
    Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.
    Type: Application
    Filed: September 18, 2015
    Publication date: August 23, 2018
    Applicant: INTEL CORPORATION
    Inventors: MARK L. DOCZY, BRIAN S. DOYLE, CHARLES C. KUO, KAAN OGUZ, KEVIN P. O'BRIEN, SATYARTH SURI, TEJASWI K. INDUKURI
  • Publication number: 20180165065
    Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) device with out-of-plane magnetizations for its free and fixed magnetic layers, and configured to have a magnetization offset away from a center and closer to a switching threshold of the MTJ device; and logic for generating random numbers according to a resistive state of the MTJ device.
    Type: Application
    Filed: June 17, 2015
    Publication date: June 14, 2018
    Inventors: Charles C. KUO, Justin S. BROCKMAN, Juan G. ALZATE VINASCO, Kaan OGUZ, Kevin P. O'BRIEN, Brian S. DOYLE, Mark L. DOCZY, Satyarth SURI, Robert S. CHAU, Prashant MAJHI, Ravi PILLARISETTY, Elijah V. KARPOV
  • Publication number: 20180166625
    Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.
    Type: Application
    Filed: January 29, 2018
    Publication date: June 14, 2018
    Applicant: INTEL CORPORATION
    Inventors: Charles C. Kuo, Kaan Oguz, Brian S. Doyle, Mark L. Doczy, David L. Kencke, Satyarth Suri, Robert S. Chau
  • Patent number: 9882121
    Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: January 30, 2018
    Assignee: INTEL CORPORATION
    Inventors: Charles C. Kuo, Kaan Oguz, Brian S. Doyle, Mark L. Doczy, David L. Kencke, Satyarth Suri, Robert S. Chau
  • Publication number: 20170345476
    Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.
    Type: Application
    Filed: September 26, 2014
    Publication date: November 30, 2017
    Applicants: Intel Corporation, Intel Corporation
    Inventors: Mark L. DOCZY, Kaan OGUZ, Brian S. DOYLE, Charles C. KUO, Robert S. CHAU, Satyarth SURI
  • Patent number: 9779794
    Abstract: Techniques are disclosed for forming a spin-transfer torque memory (STTM) element having an annular contact to reduce critical current requirements. The techniques reduce critical current requirements for a given magnetic tunnel junction (MTJ), because the annular contact reduces contact size and increases local current density, thereby reducing the current needed to switch the direction of the free magnetic layer of the MTJ. In some cases, the annular contact surrounds at least a portion of an insulator layer that prevents the passage of current. In such cases, current flows through the annular contact and around the insulator layer to increase the local current density before flowing through the free magnetic layer. The insulator layer may comprise a dielectric material, and in some cases, is a tunnel material, such as magnesium oxide (MgO). In some cases, a critical current reduction of at least 10% is achieved for a given MTJ.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: October 3, 2017
    Assignee: INTEL CORPORATION
    Inventors: Brian S. Doyle, David L. Kencke, Kaan Oguz, Mark L. Doczy, Satyarth Suri, Robert S. Chau, Charles C. Kuo, Roksana Golizadeh Mojarad
  • Publication number: 20170271578
    Abstract: A method including forming a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a fully-crystalline sacrificial film or substrate including a crystal lattice similar to the crystal lattice of the dielectric material; and transferring the device stack from the sacrificial film to a device substrate. An apparatus including a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a device substrate wherein the fixed magnetic layer and the free magnetic layer each have a crystalline lattice conforming to a crystalline lattice of the sacrificial film or substrate on which they were formed prior to transfer to the device substrate.
    Type: Application
    Filed: September 26, 2014
    Publication date: September 21, 2017
    Inventors: Kevin P. O'BRIEN, Brian S. DOYLE, Kaan OGUZ, Robert S. CHAU, Satyarth SURI
  • Publication number: 20170092846
    Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF).
    Type: Application
    Filed: July 7, 2014
    Publication date: March 30, 2017
    Applicant: INTEL CORPORATION
    Inventors: BRIAN S. DOYLE, KAAN OGUZ, CHARLES C. KUO, MARK L. DOCZY, SATYARTH SURI, DAVID L. KENCKE, ROBERT S. CHAU, ROKSANA GOLIZADEH MOJARAD
  • Publication number: 20160359101
    Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.
    Type: Application
    Filed: March 28, 2014
    Publication date: December 8, 2016
    Applicant: INTEL CORPORATION
    Inventors: CHARLES C. KUO, KAAN OGUZ, BRIAN S. DOYLE, MARK L. DOCZY, DAVID L. KENCKE, SATYARTH SURI, ROBERT S. CHAU
  • Publication number: 20160351238
    Abstract: Techniques are disclosed for forming a spin-transfer torque memory (STTM) element having an annular contact to reduce critical current requirements. The techniques reduce critical current requirements for a given magnetic tunnel junction (MTJ), because the annular contact reduces contact size and increases local current density, thereby reducing the current needed to switch the direction of the free magnetic layer of the MTJ. In some cases, the annular contact surrounds at least a portion of an insulator layer that prevents the passage of current. In such cases, current flows through the annular contact and around the insulator layer to increase the local current density before flowing through the free magnetic layer. The insulator layer may comprise a dielectric material, and in some cases, is a tunnel material, such as magnesium oxide (MgO). In some cases, a critical current reduction of at least 10% is achieved for a given MTJ.
    Type: Application
    Filed: March 26, 2014
    Publication date: December 1, 2016
    Applicant: INTEL CORPORATION
    Inventors: BRIAN S. DOYLE, DAVID L. KENCKE, KAAN OGUZ, MARK L. DOCZY, SATYARTH SURI, ROBERT S. CHAU, CHARLES C. KUO, ROKSANA GOLIZADEH MOJARAD
  • Patent number: 9496486
    Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: November 15, 2016
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, David L. Kencke, Charles C. Kuo, Uday Shah, Kaan Oguz, Mark L. Doczy, Satyarth Suri, Clair Webb
  • Patent number: 9224794
    Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Steven Keating, Nick Lindert, Nadia Rahhal-Orabi, Brian Doyle, Satyarth Suri, Swaminathan Sivakumar, Lana Jong, Lin Sha
  • Patent number: 9214215
    Abstract: Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: December 15, 2015
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Brian S. Doyle, Kaan Oguz, Satyarth Suri, Robert S. Chau, Charles S. Kuo, Mark L. Doczy, David L. Kencke