Patents by Inventor Saurabh Chopra

Saurabh Chopra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240360587
    Abstract: The present disclosure relates to a radiation reflector assembly for use with a semiconductor processing chamber and a substrate processing system having the radiation reflector assembly. The radiation reflector assembly includes a shell body that includes an interior cylindrical wall; and a reflector disk that includes a center hole, a bottom reflective surface, and a top surface. The reflector disk is disposed within and spaced from the interior cylindrical wall in a manner that permits fluid to flow therebetween. The radiation reflector assembly includes an actuator coupled to the reflector disk, and the actuator is operable to axially displace the reflector disk relative to the shell body. The radiation reflector assembly includes an elongated tube extending through the center hole of the reflector disk. A method of processing a substrate with the radiation reflector assembly is also described.
    Type: Application
    Filed: July 18, 2023
    Publication date: October 31, 2024
    Inventors: Ala MORADIAN, Vishwas Kumar PANDEY, Lori D. WASHINGTON, Saurabh CHOPRA
  • Publication number: 20240347602
    Abstract: A three-dimensional semiconductor (3D) device. The 3D device may include a substrate, and a monocrystalline layer stack. The monocrystalline layer stack may include at least one monocrystalline semiconductor layer, separated from, and disposed over a main surface of the substrate. The 3D device may further include a plurality of epitaxial heterostructures, integrally grown from the at least one monocrystalline semiconductor layer. As such, a first epitaxial heterostructure may be disposed on a lower surface of the at least one monocrystalline semiconductor layer, facing the substrate, and wherein a second epitaxial heterostructure may be disposed on an upper surface of the monocrystalline semiconductor layer, opposite the lower surface.
    Type: Application
    Filed: April 10, 2024
    Publication date: October 17, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Fredrick FISHBURN, Balasubramanian PRANATHARTHIHARAN, Abhishek DUBE, Saurabh CHOPRA
  • Publication number: 20240301584
    Abstract: A process for cleaning a substrate includes removing carbon containing contaminants from a native oxide layer on a surface of a substrate by performing a reducing process using a hydrogen containing plasma, and after removing carbon containing contaminants, removing the native oxide layer from the substrate by performing an etch process using a fluorine containing plasma.
    Type: Application
    Filed: May 17, 2024
    Publication date: September 12, 2024
    Inventors: Christopher S. OLSEN, Theresa K. GUARINI, Jeffrey TOBIN, Lara HAWRYLCHAK, Peter STONE, Chi Wei LO, Saurabh CHOPRA
  • Patent number: 12068155
    Abstract: Embodiments described herein relate to a method of epitaxial deposition of p-channel metal oxide semiconductor (MMOS) source/drain regions within horizontal gate all around (hGAA) device structures. Combinations of precursors are described herein, which grow of the source/drain regions on predominantly <100> surfaces with reduced or negligible growth on <110> surfaces. Therefore, growth of the source/drain regions is predominantly located on the top surface of a substrate instead of the alternating layers of the hGAA structure. The precursor combinations include a silicon containing precursor, a germanium containing precursor, and a boron containing precursor. At least one of the precursors further includes chlorine.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: August 20, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Chen-Ying Wu, Zhiyuan Ye, Xuebin Li, Sathya Chary, Yi-Chiau Huang, Saurabh Chopra
  • Publication number: 20240248298
    Abstract: Embodiments herein are generally directed to electronic device manufacturing and, more particularly, to systems and methods for lamp heating in thermal processing chambers. In an embodiment, an adjustable reflector assembly includes a plurality of elements including at least one stationary element and at least one rotating element, wherein a first surface of each of the plurality of elements is a reflective surface, and at least one actuation mechanism configured to actuate the at least one rotating element relative to the stationary element. A method of processing a substrate includes measuring a thermal intensity of a thermal profile of an area of a substrate under a lamp and the reflector assembly, determining if the thermal intensity is outside of desired parameters, and in response to the thermal intensity being outside of desired parameters, and adjusting a reflector profile of the reflector assembly.
    Type: Application
    Filed: January 25, 2023
    Publication date: July 25, 2024
    Inventors: Ala MORADIAN, Saurabh CHOPRA, Lori D. WASHINGTON
  • Publication number: 20240248282
    Abstract: Embodiments herein are generally directed to electronic device manufacturing and, more particularly, to systems and methods for lamp heating in thermal processing chambers. In one embodiment, a substrate processing chamber includes a lid, a floor, and a processing volume between the lid and the floor. An upper window is disposed between the lid and the processing volume, a lower window is disposed between the floor and the processing volume. A lamp head is disposed between the lower window and the floor or between the upper window and the lid. At least one lamp is disposed within the lamp head, and a lens is disposed between the lamp head and the processing volume. In another embodiment, a plurality of lamps is disposed within the lamp head including at least one first lamp operating at a first wavelength and at least one second lamp operating at a second wavelength.
    Type: Application
    Filed: January 25, 2023
    Publication date: July 25, 2024
    Inventors: Ala MORADIAN, Saurabh CHOPRA, Lori D. WASHINGTON
  • Publication number: 20240248297
    Abstract: Embodiments herein are generally directed to electronic device manufacturing and, more particularly, to systems and methods for lamp heating in thermal processing chambers. In an embodiment, an adjustable reflector includes a plurality of reflector elements. Each of the plurality of elements as a first surface, a second surface, and a plurality of sidewalls. The first surface is a reflective surface and is configured to face a lamp. The adjustable reflector includes one or more actuation mechanisms coupled to the plurality of elements. A method of thermally processing a substrate includes measuring a thermal intensity of a thermal profile of an area of a substrate under or over a lamp and the adjustable reflector, and in response to the thermal intensity being outside of desired parameters, adjusting the reflector profile of the reflector assembly along a centerline path.
    Type: Application
    Filed: January 25, 2023
    Publication date: July 25, 2024
    Inventors: Ala MORADIAN, Saurabh CHOPRA, Lori D. WASHINGTON
  • Publication number: 20240234175
    Abstract: The present disclosure relates to heat source arrangements, processing chambers, and related methods to facilitate deposition process adjustability. In one implementation, a processing chamber applicable for use in semiconductor manufacturing includes a lower window and an upper window. The lower window and the upper window at least partially define an internal volume. The processing chamber includes a substrate support disposed in the internal volume, and the substrate support includes a support face. The processing chamber includes one or more inner heat sources. Each inner heat source of the one or more inner heat sources is oriented substantially parallel to a surface of the support face. The processing chamber includes one or more outer heat sources disposed outwardly of the inner heat sources. Each outer heat source of the one or more outer heat sources is oriented nonparallel to the surface of the support face.
    Type: Application
    Filed: October 21, 2022
    Publication date: July 11, 2024
    Inventors: Ala MORADIAN, Saurabh CHOPRA
  • Publication number: 20240136207
    Abstract: The present disclosure relates to heat source arrangements, processing chambers, and related methods to facilitate deposition process adjustability. In one implementation, a processing chamber applicable for use in semiconductor manufacturing includes a lower window and an upper window. The lower window and the upper window at least partially define an internal volume. The processing chamber includes a substrate support disposed in the internal volume, and the substrate support includes a support face. The processing chamber includes one or more inner heat sources. Each inner heat source of the one or more inner heat sources is oriented substantially parallel to a surface of the support face. The processing chamber includes one or more outer heat sources disposed outwardly of the inner heat sources. Each outer heat source of the one or more outer heat sources is oriented nonparallel to the surface of the support face.
    Type: Application
    Filed: October 20, 2022
    Publication date: April 25, 2024
    Inventors: Ala MORADIAN, Saurabh CHOPRA
  • Patent number: 11965241
    Abstract: In one aspect, a process operation is conducted at a first pressure in a process chamber, and an epitaxial deposition operation is conducted at an atmospheric pressure in an epitaxial deposition chamber. The atmospheric pressure is greater than the first pressure. The process chamber is mounted to a first mainframe that operates at the first pressure (a reduced pressure), and the epitaxial deposition chamber is mounted to a second mainframe that operates at the atmospheric chamber. In one aspect, the process chamber is a cleaning chamber (such as a pre-clean chamber) and the process operation is a cleaning operation. In one aspect, the process chamber is an atmospheric pressure epitaxial deposition chamber and the process operation is an atmospheric pressure epitaxial deposition operation.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: April 23, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Saurabh Chopra, Martin Jeffrey Salinas, Masato Ishii, Sheng-Chen Twan, Srividya Natarajan
  • Patent number: 11948796
    Abstract: One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {100} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {110} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: April 2, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yi-Chiau Huang, Chen-Ying Wu, Abhishek Dube, Chia Cheng Chin, Saurabh Chopra
  • Publication number: 20240088222
    Abstract: A processing system includes one or more processing chambers, and a system controller configured to cause the processing system to perform (a) a pre-clean process on exposed surfaces of a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region, (b) a first deposition process to form an amorphous silicon-containing layer on the exposed surfaces of the semiconductor structure, (c) a recrystallization anneal process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer within the trench, (d) an etch process to remove remaining portions of the amorphous silicon-containing layer, and (e) a second deposition process, to epitaxially form a source/drain region over the silicon-containing crystalline layer wi
    Type: Application
    Filed: September 12, 2022
    Publication date: March 14, 2024
    Inventors: Shawn THOMAS, Saurabh CHOPRA, John TOLLE
  • Patent number: 11887079
    Abstract: A method and system for central hub reconciliation is disclosed. The central hub reconciliation can provide for improved methods of reconciliation between a buyer (e.g., a request realization party) and a supplier (e.g., a request originating party). A central hub server may receive a data file comprising remittance data and payment data from a request realization computer. The remittance data is associated with a request provided from a request originating computer to the request realization computer. The central hub server ay then generate a unique identifier for the data file, and provide the payment data and the unique identifier to an authorizing entity computer requesting payment on behalf of the request realization computer. The central hub provides the remittance data and the unique identifier to the request originating computer which updates a repository using the payment data and the remittance data upon finding a match.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: January 30, 2024
    Assignee: Visa International Service Association
    Inventors: Alexander Godshall, Ximena Bellido Hoefken, Juliette Metzger, Khyati Shah, Saurabh Chopra
  • Publication number: 20240018688
    Abstract: The present disclosure relates to batch processing apparatus, systems, and related methods and structures for epitaxial deposition operations. In one implementation, an apparatus for substrate processing includes a chamber body. The chamber body includes a processing volume, a plurality of gas inject passages, and an exhaust port. The apparatus includes one or more upper heat sources positioned above the processing volume, one or more lower heat sources positioned below the processing volume, and a pedestal assembly positioned in the processing volume. The apparatus includes one or more side heat sources positioned outwardly of the processing volume and configured to heat the processing volume through a side of the processing volume. The chamber body can be a dual-chamber body that includes a second processing volume, and the one or more side heat sources can be positioned outwardly of one or more of the processing volume or the second processing volume.
    Type: Application
    Filed: December 2, 2022
    Publication date: January 18, 2024
    Inventors: Errol Antonio C. SANCHEZ, Shu-Kwan LAU, Zuoming ZHU, Saurabh CHOPRA, Abhishek DUBE, Chandra MOHAPATRA, Alexandros ANASTASOPOULOS, Martin Jeffrey SALINAS
  • Publication number: 20240018658
    Abstract: The present disclosure relates to flow guide structures and heat shield structures, and related methods, for deposition uniformity and process adjustability. In one implementation, an apparatus for substrate processing includes a chamber body that includes a processing volume. The apparatus includes one or more heat sources. The apparatus includes a flow guide structure positioned in the processing volume. The flow guide structure includes one or more first flow dividers that divide the processing volume into a plurality of flow levels, and one or more second flow dividers oriented to intersect the one or more first flow dividers and divide each flow level of the plurality of flow levels into a plurality of flow sections. The flow guide structure includes one or more third flow dividers oriented to intersect the one or more second flow dividers and divide the plurality of flow sections into a plurality of flow zones.
    Type: Application
    Filed: December 20, 2022
    Publication date: January 18, 2024
    Inventors: Zuoming ZHU, Ala MORADIAN, Shu-Kwan LAU, John TOLLE, Manjunath SUBBANNA, Martin Jeffrey SALINAS, Chia Cheng CHIN, Thomas KIRSCHENHEITER, Saurabh CHOPRA
  • Patent number: 11636490
    Abstract: Provided are computer-implemented methods for linking accounts across systems which may include receiving an authorization request message including transaction data associated with a payment transaction and a primary account number (PAN); identifying a token corresponding to the PAN; transmitting a request message comprising at least a portion of the transaction data associated with the payment transaction and the token to at least one employer system, wherein the at least one employer system is associated with at least one employer institution; and receiving, from the at least one employer system, at least one response message comprising transaction adjustment data associated with an adjustment to the payment transaction. Methods may also include adjusting at least one parameter of the payment transaction based at least partially on the transaction adjustment data. Systems and computer program products are also provided.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: April 25, 2023
    Assignee: Visa International Service Association
    Inventors: Jeffrey Moore, Saurabh Chopra, Luba Goldberg, Darcy Montgomery Andrews, Claire Taitague Feeley
  • Publication number: 20230075715
    Abstract: In one aspect, a process operation is conducted at a first pressure in a process chamber, and an epitaxial deposition operation is conducted at an atmospheric pressure in an epitaxial deposition chamber. The atmospheric pressure is greater than the first pressure. The process chamber is mounted to a first mainframe that operates at the first pressure (a reduced pressure), and the epitaxial deposition chamber is mounted to a second mainframe that operates at the atmospheric chamber. In one aspect, the process chamber is a cleaning chamber (such as a pre-clean chamber) and the process operation is a cleaning operation. In one aspect, the process chamber is an atmospheric pressure epitaxial deposition chamber and the process operation is an atmospheric pressure epitaxial deposition operation.
    Type: Application
    Filed: July 20, 2022
    Publication date: March 9, 2023
    Inventors: Saurabh CHOPRA, Martin Jeffrey SALINAS, Masato ISHII, Sheng-Chen TWAN, Srividya NATARAJAN
  • Publication number: 20230040606
    Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is crystallized. Epitaxially growth of the source and drain regions then proceeds, which growth advantageously occurring on the bottom and sidewalls of the source and drain regions.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 9, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Benjamin Colombeau, Saurabh Chopra, Myungsun Kim, Balasubramanian Pranatharthiharan
  • Publication number: 20230037320
    Abstract: Embodiments described herein relate to a method of epitaxial deposition of p-channel metal oxide semiconductor (MMOS) source/drain regions within horizontal gate all around (hGAA) device structures. Combinations of precursors are described herein, which grow of the source/drain regions on predominantly <100> surfaces with reduced or negligible growth on <110> surfaces. Therefore, growth of the source/drain regions is predominantly located on the top surface of a substrate instead of the alternating layers of the hGAA structure. The precursor combinations include a silicon containing precursor, a germanium containing precursor, and a boron containing precursor. At least one of the precursors further includes chlorine.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 9, 2023
    Inventors: Chen-Ying WU, Zhiyuan YE, Xuebin LI, Sathya CHARY, Yi-Chiau HUANG, Saurabh CHOPRA
  • Publication number: 20220375751
    Abstract: Embodiments of the present disclosure generally relate to an integrated substrate processing system for cleaning a substrate surface and subsequently performing an epitaxial deposition process thereon. A processing system includes a film formation chamber, a transfer chamber coupled to the film formation chamber, and an oxide removal chamber coupled to the transfer chamber, the oxide removal chamber having a substrate support. The processing system includes a controller configured to introduce a process gas mixture into the oxide removal chamber, the process gas mixture including a fluorine-containing gas and a vapor including at least one of water, an alcohol, an organic acid, or combinations thereof. The controller is configured to expose a substrate positioned on the substrate support to the process gas mixture, thereby removing an oxide film from the substrate.
    Type: Application
    Filed: September 1, 2021
    Publication date: November 24, 2022
    Inventors: Yi-Chiau HUANG, Songjae Lee, Manoj Vellaikal, Chen-Ying Wu, Eric Davey, Saurabh Chopra