Patents by Inventor Saurabh Singh

Saurabh Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11557690
    Abstract: Semitransparent chalcogen solar cells and techniques for fabrication thereof are provided. In one aspect, a method of forming a solar cell includes: forming a first transparent contact on a substrate; depositing an n-type layer on the first transparent contact; depositing a p-type chalcogen absorber layer on the n-type layer, wherein a p-n junction is formed between the p-type chalcogen absorber layer and the n-type layer; depositing a protective interlayer onto the p-type chalcogen absorber layer, wherein the protective interlayer fully covers the p-type chalcogen absorber layer; and forming a second transparent contact on the interlayer, wherein the interlayer being disposed between the p-type chalcogen absorber layer and the second transparent contact serves to protect the p-n junction during the forming of the second transparent contact. Solar cells and other methods for formation thereof are also provided.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Douglas M. Bishop, Yun Seog Lee, Saurabh Singh, Teodor K. Todorov
  • Publication number: 20230003779
    Abstract: A method for estimating resistances of a circuit having a plurality of resistances comprising a first resistance and a second resistance may include applying a first bias voltage across the circuit and measuring a first voltage at a common node between the first resistance and the second resistance in order to determine a mathematical relationship between the first resistance and the second resistance, applying a second bias voltage across the circuit and a third resistance in parallel with the circuit and measuring a second voltage at the common node between the first resistance and the second resistance in order to determine a mathematical relationship between the third resistance and at least one of the first resistance and the second resistance, and based on at least the measurement of the first voltage and the measurement of the second voltage, determining the first resistance and the second resistance as a function of the third resistance.
    Type: Application
    Filed: February 10, 2022
    Publication date: January 5, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Saurabh SINGH, Chandra B. PRAKASH, Eric KIMBALL, Cory J. PETERSON, Ryan LOBO
  • Patent number: 11538197
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for channel-wise autoregressive entropy models. In one aspect, a method includes processing data using a first encoder neural network to generate a latent representation of the data. The latent representation of data is processed by a quantizer and a second encoder neural network to generate a quantized latent representation of data and a latent representation of an entropy model. The latent representation of data is further processed into a plurality of slices of quantized latent representations of data wherein the slices are arranged in an ordinal sequence. A hyperprior processing network generates a hyperprior parameters and a compressed representation of the hyperprior parameters. For each slice, a corresponding compressed representation is generated using a corresponding slice processing network wherein a combination of the compressed representations form a compressed representation of the data.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: December 27, 2022
    Assignee: Google LLC
    Inventors: David Charles Minnen, Saurabh Singh
  • Patent number: 11536767
    Abstract: The present disclosure relates to self-test circuitry for a system that includes one or more current control subsystems, each current control subsystem having a load terminal for coupling the current control subsystem to a load. The self-test circuitry comprises: a signal path associated with each current control subsystem, each signal path configured to selectively couple a measurement node to the load terminal of the current control subsystem, wherein the measurement node is common to all of the signal paths; voltage detection circuitry; and test voltage source circuitry configured to provide a test voltage to the measurement node. The voltage detection circuitry is operable to output a signal indicative of a fault condition if a voltage detected at the measurement node differs from the test voltage when the measurement node is coupled to the load terminal.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: December 27, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: James Wells, Saurabh Singh, Huy Binh Le, Gavin Wilson, Niall McGurnaghan, Simon R. Foster, Mark McCloy-Stevens
  • Patent number: 11526744
    Abstract: Methods, apparatuses, and embodiments related to a technique for monitoring construction of a structure. In an example, a robot with a sensor, such as a LIDAR device, enters a building and obtains sensor readings of the building. The sensor data is analyzed and components related to the building are identified. The components are mapped to corresponding components of an architect's three dimensional design of the building, and the installation of the components is checked for accuracy. When a discrepancy above a certain threshold is detected, an error is flagged and project managers are notified. Construction progress updates do not give credit for completed construction that includes an error, resulting in improved accuracy progress updates and corresponding improved accuracy for project schedule and cost estimates.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 13, 2022
    Assignee: Doxel, Inc.
    Inventors: Saurabh Ladha, Robin Singh
  • Publication number: 20220391128
    Abstract: Example compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store look-up-table (LUT) entries for use in a multiply and accumulate (MAC) operation.
    Type: Application
    Filed: June 7, 2021
    Publication date: December 8, 2022
    Inventors: Saurabh JAIN, Srivatsa RANGACHAR SRINIVASA, Akshay Krishna RAMANATHAN, Gurpreet Singh KALSI, Kamlesh R. PILLAI, Sreenivas SUBRAMONEY
  • Patent number: 11507710
    Abstract: This disclosure relates generally to system and method for optimization of industrial processes, for example a tundish process. Typically geometries for industrial processes are simulated in a numerical analysis model such as a CFD. In order to simulate a physical phenomenon (such as tundish process) numerically, the domain thereof is discretized in order to convert the differential equations to be solved in the domain into linear equations. The accuracy of a CFD solution is dependent on a mesh of the domain, which in turn depends on a geometry thereof. For setting up an optimization task, the disclosed method provides first a CFD friendly base geometry, so that a faulty geometry can be detected before forming the complete geometry.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: November 22, 2022
    Assignee: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Prateek Singh, Dilshad Ahmad, Saurabh Mangal
  • Publication number: 20220347604
    Abstract: A filter assembly that comprises a housing, an outer filter element, and an inner filter element. The outer filter element is positionable within the housing and comprises an outer filter media. The inner filter element is positionable within the outer filter element and comprises an inner filter media, a media support structure, an inner top endplate, and an inner bottom endplate. The inner top endplate comprising a top rib that extends continuously around a portion of a top surface of the inner top endplate.
    Type: Application
    Filed: July 7, 2022
    Publication date: November 3, 2022
    Applicant: Cummins Filtration IP, Inc.
    Inventors: Manikandan Annamalai, Saurabh Saboo, Jayant Singh, Zemin Jiang, Prashant Ramesh Khedkar, Kevin C. South
  • Publication number: 20220353970
    Abstract: The present disclosure relates to current control circuitry for controlling a current through a load, the current control circuitry comprising: amplifier circuitry; reference voltage generator circuitry configured to supply a fixed reference voltage to a first input of the amplifier circuitry; an output stage comprising: a control terminal coupled to an output of the amplifier circuitry; a current input terminal configured to be coupled to the load; a current output terminal; a clock-controlled variable resistance coupled to the current output terminal of the output stage, wherein a resistance of the variable resistance is based on a digital code input to the variable resistance; and a feedback path between the current output terminal of the output stage and a second terminal of the amplifier circuitry for providing a feedback voltage to a second input of the amplifier circuitry.
    Type: Application
    Filed: July 8, 2022
    Publication date: November 3, 2022
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Dave SMITH, Saurabh SINGH, Andrew BUIST, Paulius CEREBIEJUS, Mark J. MCCLOY-STEVENS, Terence A. ORR
  • Publication number: 20220343167
    Abstract: A method of performing federated feature selection for a machine learning model in a federated learning environment includes obtaining, at a first resolution, a global set of selector neural network weights. At a second resolution, the method selects, for a plurality of first data subsets, a first set of features from a feature space by iteratively applying a first selector neural network that is initialized with the global set of selector neural network weights to the first data subset to obtain a first set of selector neural network weights. The first data subsets are divided into a plurality of second data subsets, and, at a third resolution, a second set of features is selected from the feature space.
    Type: Application
    Filed: October 30, 2020
    Publication date: October 27, 2022
    Inventors: Deepa CHAWLA, Gaurav DIXIT, Wenfeng HU, Selim ICKIN, Farnaz MORADI, Erik SANDERS, Saurabh SINGH, Jalil TAGHIA, Konstantinos VANDIKAS
  • Publication number: 20220333239
    Abstract: A heat shield for a platen of a substrate support includes a body and absorption-reflection-transmission regions. The absorption-reflection-transmission regions are in contact with the body and are configured to at least one of affect or modulate at least a portion of a heat flux pattern between a distal reference surface and the platen. The absorption-reflection-transmission regions include tunable aspects to tune the at least a portion of the heat flux pattern.
    Type: Application
    Filed: September 24, 2020
    Publication date: October 20, 2022
    Inventors: Ashish SAURABH, Karl Frederick LEESER, Xinyi CHEN, Mukesh Dhami SINGH, Troy GOMM, Timothy Scott THOMAS, Curtis W. BAILEY
  • Patent number: 11477868
    Abstract: The present disclosure relates to current control circuitry for controlling a current through a load. The current control circuitry comprises amplifier circuitry, reference voltage generator circuitry configured to supply a fixed reference voltage to a first input of the amplifier circuitry and an output stage comprising: a control terminal coupled to an output of the amplifier circuitry; a current input terminal configured to be coupled to the load; and a current output terminal. The current control circuitry further comprises a variable resistance coupled to the current output terminal of the output stage, and a feedback path between the current output terminal of the output stage and a second terminal of the amplifier circuitry for providing a feedback voltage to a second input of the amplifier circuitry.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: October 18, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Dave Smith, Saurabh Singh, Andrew Buist, Paulius Cerebiejus, Mark J. McCloy-Stevens, Terence A. Orr
  • Publication number: 20220283246
    Abstract: A method of detecting a defect in a connecting member of a radio unit in a radio site includes applying an artificial radio traffic load to a first radio unit and at least a second radio unit, such that the radio traffic load experienced by the first and the second radio unit is at a same level, measuring power supplied to the first radio unit via a first connecting member and power supplied to the second radio unit via a second connecting member at an end of each connecting member terminating at a device configured to supply power to the radio units, and determining from the measured power and an expected nominal power loss of the first and the second connecting member if there is power loss in at least one of the first and the second connecting member indicating a defect.
    Type: Application
    Filed: August 9, 2019
    Publication date: September 8, 2022
    Inventors: Lackis ELEFTHERIADIS, Bin SUN, Xiaoyu LAN, Saurabh SINGH, Erik SANDERS, Marios DAOUTIS
  • Patent number: 11411191
    Abstract: Selenium-fullerene heterojunction solar cells and techniques for fabrication thereof are provided. In one aspect, a method of forming a solar cell includes: forming a front contact on a substrate; depositing an n-type semiconducting layer on the front contact, wherein the n-type semiconducting layer comprises a fullerene or fullerene derivative; forming a p-type chalcogen absorber layer on the n-type semiconducting layer; depositing a high workfunction material onto the p-type chalcogen absorber layer, wherein the high workfunction material has a workfunction of greater than about 5.2 electron volts; and forming a back contact on the high workfunction material. Solar cells and other methods for formation thereof are also provided.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 9, 2022
    Assignee: International Business Machines Corporation
    Inventors: Douglas M. Bishop, Yun Seog Lee, Saurabh Singh, Teodor K. Todorov
  • Patent number: 11389753
    Abstract: A filter assembly that comprises a housing, an outer filter element, and an inner filter element. The outer filter element is positionable within the housing and comprises an outer filter media. The inner filter element is positionable within the outer filter element and comprises an inner filter media, a media support structure, an inner top endplate, and an inner bottom endplate. The inner top endplate comprising a top rib that extends continuously around a portion of a top surface of the inner top endplate.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: July 19, 2022
    Assignee: CUMMINS FILTRATION IP, INC.
    Inventors: Manikandan Annamalai, Saurabh Saboo, Jayant Singh, Zemin Jiang, Prashant Ramesh Khedkar, Kevin C. South
  • Patent number: 11383185
    Abstract: A filter assembly that comprises a housing, an outer filter element, and an inner filter element. The outer filter element is positionable within the housing and comprises an outer filter media. The inner filter element is positionable within the outer filter element and comprises an inner filter media, a media support structure, an inner top endplate, and an inner bottom endplate. The inner top endplate comprising a top rib that extends continuously around a portion of a top surface of the inner top endplate.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: July 12, 2022
    Assignee: CUMMINS FILTRATION IP, INC.
    Inventors: Manikandan Annamalai, Saurabh Saboo, Jayant Singh, Zemin Jiang, Prashant Ramesh Khedkar, Kevin C. South
  • Patent number: 11372724
    Abstract: A method and system are provided for handling a blockchain network based file storage system including a plurality of electronic devices.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: June 28, 2022
    Inventors: Vipul Gupta, Ankur Agrawal, Rahul Agrawal, Prashant Sharma, Kalgesh Singh, Saurabh Kumar, Anil Kumar Saini
  • Patent number: 11354822
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for image compression and reconstruction. A request to generate an encoded representation of an input image is received. The encoded representation of the input image is then generated. The encoded representation includes a respective set of binary codes at each iteration. Generating the set of binary codes for the iteration from an initial set of binary includes: for any tiles that have already been masked off during any previous iteration, masking off the tile. For any tiles that have not yet been masked off during any of the previous iterations, a determination is made as to whether a reconstruction error of the tile when reconstructed from binary codes at the previous iterations satisfies an error threshold. When the reconstruction quality satisfies the error threshold, the tile is masked off.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: June 7, 2022
    Assignee: Google LLC
    Inventors: Michele Covell, Damien Vincent, David Charles Minnen, Saurabh Singh, Sung Jin Hwang, Nicholas Johnston, Joel Eric Shor, George Dan Toderici
  • Publication number: 20220138991
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for compressing and decompressing data. In one aspect, a method comprises: processing data using an encoder neural network to generate a latent representation of the data; processing the latent representation of the data using a hyper-encoder neural network to generate a latent representation of an entropy model; generating an entropy encoded representation of the latent representation of the entropy model; generating an entropy encoded representation of the latent representation of the data using the latent representation of the entropy model; and determining a compressed representation of the data from the entropy encoded representations of: (i) the latent representation of the data and (ii) the latent representation of the entropy model used to entropy encode the latent representation of the data.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Inventors: David Charles Minnen, Saurabh Singh, Johannes Balle, Troy Chinen, Sung Jin Hwang, Nicholas Johnston, George Dan Toderici
  • Patent number: 11316523
    Abstract: A system may include a digitally-controlled oscillator configured to generate an output clock signal based on a control signal received at an input of the digitally-controlled oscillator and a control circuit configured to calculate an error signal between the output clock signal and an external reference clock signal, filter the error signal to generate a correction signal, generate the control signal based on the correction signal, and switch between a first mode of operation and a second mode of operation without artifacts on the correction signal during switching between the first mode and the second mode.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: April 26, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Saurabh Singh, Jaimin Mehta, Sriram Balasubramanian, Anindya Bhattacharya