Patents by Inventor Saurabh Singh

Saurabh Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230186166
    Abstract: Example aspects of the present disclosure are directed to systems and methods that learn a compressed representation of a machine-learned model (e.g., neural network) via representation of the model parameters within a reparameterization space during training of the model. In particular, the present disclosure describes an end-to-end model weight compression approach that employs a latent-variable data compression method. The model parameters (e.g., weights and biases) are represented in a “latent” or “reparameterization” space, amounting to a reparameterization. In some implementations, this space can be equipped with a learned probability model, which is used first to impose an entropy penalty on the parameter representation during training, and second to compress the representation using arithmetic coding after training. The proposed approach can thus maximize accuracy and model compressibility jointly, in an end-to-end fashion, with the rate-error trade-off specified by a hyperparameter.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Inventors: Deniz Oktay, Saurabh Singh, Johannes Balle, Abhinav Shrivistava
  • Patent number: 11670010
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for compressing and decompressing data. In one aspect, a method comprises: processing data using an encoder neural network to generate a latent representation of the data; processing the latent representation of the data using a hyper-encoder neural network to generate a latent representation of an entropy model; generating an entropy encoded representation of the latent representation of the entropy model; generating an entropy encoded representation of the latent representation of the data using the latent representation of the entropy model; and determining a compressed representation of the data from the entropy encoded representations of: (i) the latent representation of the data and (ii) the latent representation of the entropy model used to entropy encode the latent representation of the data.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: June 6, 2023
    Assignee: Google LLC
    Inventors: David Charles Minnen, Saurabh Singh, Johannes Balle, Troy Chinen, Sung Jin Hwang, Nicholas Johnston, George Dan Toderici
  • Publication number: 20230168973
    Abstract: An intermittent network connection between a source system and a destination system is established by establishing a first connection from a management resource to a first port of the destination system, causing a second port of the destination system to be enabled including by proving an instruction via the first connection to the first port of the destination system, establishing a second connection from the management resource to a first port of a source system, causing a second port of the source system to be enabled including by providing an instruction via the second connection to the first port of the source system, registering the destination system with the source system, and causing a third connection to be established between the second port of the source system and the second port of the destination system for transferring data from the source system to the destination system.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 1, 2023
    Inventors: Karthick Radhakrishnan, Saurabh Singh
  • Publication number: 20230154051
    Abstract: Systems and methods are directed to encoding and/or decoding of the textures/geometry of a three-dimensional volumetric representation. An encoding computing system can obtain voxel blocks from a three-dimensional volumetric representation of an object. The encoding computing system can encode voxel blocks with a machine-learned voxel encoding model to obtain encoded voxel blocks. The encoding computing system can decode the encoded voxel blocks with a machine-learned voxel decoding model to obtain reconstructed voxel blocks. The encoding computing system can generate a reconstructed mesh representation of the object based at least in part on the one or more reconstructed voxel blocks. The encoding computing system can encode textures associated with the voxel blocks according to an encoding scheme and based at least in part on the reconstructed mesh representation of the object to obtain encoded textures.
    Type: Application
    Filed: April 17, 2020
    Publication date: May 18, 2023
    Inventors: Danhang Tang, Saurabh Singh, Cem Keskin, Phillip Andrew Chou, Christian Haene, Mingsong Dou, Sean Ryan Francesco Fanello, Jonathan Taylor, Andrea Tagliasacchi, Philip Lindsley Davidson, Yinda Zhang, Onur Gonen Guleryuz, Shahram Izadi, Sofien Bouaziz
  • Patent number: 11644493
    Abstract: A method for estimating resistances of a circuit having a plurality of resistances comprising a first resistance and a second resistance may include applying a first bias voltage across the circuit and measuring a first voltage at a common node between the first resistance and the second resistance in order to determine a mathematical relationship between the first resistance and the second resistance, applying a second bias voltage across the circuit and a third resistance in parallel with the circuit and measuring a second voltage at the common node between the first resistance and the second resistance in order to determine a mathematical relationship between the third resistance and at least one of the first resistance and the second resistance, and based on at least the measurement of the first voltage and the measurement of the second voltage, determining the first resistance and the second resistance as a function of the third resistance.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: May 9, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: Saurabh Singh, Chandra B. Prakash, Eric Kimball, Cory J. Peterson, Ryan Lobo
  • Patent number: 11610124
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for receiving, by a neural network (NN), a dataset for generating features from the dataset. A first set of features is computed from the dataset using at least a feature layer of the NN. The first set of features i) is characterized by a measure of informativeness; and ii) is computed such that a size of the first set of features is compressible into a second set of features that is smaller in size than the first set of features and that has a same measure of informativeness as the measure of informativeness of the first set of features. The second set of features if generated from the first set of features using a compression method that compresses the first set of features to generate the second set of features.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: March 21, 2023
    Assignee: Google LLC
    Inventors: Abhinav Shrivastava, Saurabh Singh, Johannes Balle, Sami Ahmad Abu-El-Haija, Nicholas Johnston, George Dan Toderici
  • Publication number: 20230041074
    Abstract: A method performed by a central server node in a distributed machine learning environment is provided. The method includes: managing distributed machine learning for a plurality of local client nodes, such that a first set of the plurality of local client nodes are assigned to assist training of a first central model and a second set of the plurality of local client nodes are assigned to assist training of a second central model; obtaining information regarding network conditions for the plurality of local client nodes; clustering the plurality of local client nodes into one or more clusters based at least in part on the information regarding network conditions; re-assigning a local client node in the first set to the second set based on the clustering; and sending to the local client node a message including model weights for the second central model.
    Type: Application
    Filed: January 10, 2020
    Publication date: February 9, 2023
    Applicant: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Farnaz MORADI, Saurabh SINGH, Selim ICKIN, Wenfeng HU
  • Patent number: 11574232
    Abstract: Example aspects of the present disclosure are directed to systems and methods that learn a compressed representation of a machine-learned model (e.g., neural network) via representation of the model parameters within a reparameterization space during training of the model. In particular, the present disclosure describes an end-to-end model weight compression approach that employs a latent-variable data compression method. The model parameters (e.g., weights and biases) are represented in a “latent” or “reparameterization” space, amounting to a reparameterization. In some implementations, this space can be equipped with a learned probability model, which is used first to impose an entropy penalty on the parameter representation during training, and second to compress the representation using arithmetic coding after training. The proposed approach can thus maximize accuracy and model compressibility jointly, in an end-to-end fashion, with the rate-error trade-off specified by a hyperparameter.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: February 7, 2023
    Assignee: GOOGLE LLC
    Inventors: Deniz Oktay, Saurabh Singh, Johannes Balle, Abhinav Shrivastava
  • Publication number: 20230031363
    Abstract: A method may include receiving, by a calibration circuit, an output of a subsystem comprising the sensor and the analog front end. The method may further include separating the output individually into the sensor offset and the amplifier offset by using inherent properties of separate frequency ranges for the sensor offset and the amplifier offset. The method may also include calibrating, by the calibration circuit, the sensor offset by determining a first calibration value for the sensor offset such that the output approximates zero during an idle-channel condition. The method may additionally include calibrating, by the calibration circuit, the amplifier offset by determining a second calibration value for the amplifier offset such that the output approximates zero during the idle-channel condition.
    Type: Application
    Filed: January 11, 2022
    Publication date: February 2, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Saurabh SINGH, Chandra B. PRAKASH
  • Patent number: 11557690
    Abstract: Semitransparent chalcogen solar cells and techniques for fabrication thereof are provided. In one aspect, a method of forming a solar cell includes: forming a first transparent contact on a substrate; depositing an n-type layer on the first transparent contact; depositing a p-type chalcogen absorber layer on the n-type layer, wherein a p-n junction is formed between the p-type chalcogen absorber layer and the n-type layer; depositing a protective interlayer onto the p-type chalcogen absorber layer, wherein the protective interlayer fully covers the p-type chalcogen absorber layer; and forming a second transparent contact on the interlayer, wherein the interlayer being disposed between the p-type chalcogen absorber layer and the second transparent contact serves to protect the p-n junction during the forming of the second transparent contact. Solar cells and other methods for formation thereof are also provided.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Douglas M. Bishop, Yun Seog Lee, Saurabh Singh, Teodor K. Todorov
  • Publication number: 20230003779
    Abstract: A method for estimating resistances of a circuit having a plurality of resistances comprising a first resistance and a second resistance may include applying a first bias voltage across the circuit and measuring a first voltage at a common node between the first resistance and the second resistance in order to determine a mathematical relationship between the first resistance and the second resistance, applying a second bias voltage across the circuit and a third resistance in parallel with the circuit and measuring a second voltage at the common node between the first resistance and the second resistance in order to determine a mathematical relationship between the third resistance and at least one of the first resistance and the second resistance, and based on at least the measurement of the first voltage and the measurement of the second voltage, determining the first resistance and the second resistance as a function of the third resistance.
    Type: Application
    Filed: February 10, 2022
    Publication date: January 5, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Saurabh SINGH, Chandra B. PRAKASH, Eric KIMBALL, Cory J. PETERSON, Ryan LOBO
  • Patent number: 11536767
    Abstract: The present disclosure relates to self-test circuitry for a system that includes one or more current control subsystems, each current control subsystem having a load terminal for coupling the current control subsystem to a load. The self-test circuitry comprises: a signal path associated with each current control subsystem, each signal path configured to selectively couple a measurement node to the load terminal of the current control subsystem, wherein the measurement node is common to all of the signal paths; voltage detection circuitry; and test voltage source circuitry configured to provide a test voltage to the measurement node. The voltage detection circuitry is operable to output a signal indicative of a fault condition if a voltage detected at the measurement node differs from the test voltage when the measurement node is coupled to the load terminal.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: December 27, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: James Wells, Saurabh Singh, Huy Binh Le, Gavin Wilson, Niall McGurnaghan, Simon R. Foster, Mark McCloy-Stevens
  • Patent number: 11538197
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for channel-wise autoregressive entropy models. In one aspect, a method includes processing data using a first encoder neural network to generate a latent representation of the data. The latent representation of data is processed by a quantizer and a second encoder neural network to generate a quantized latent representation of data and a latent representation of an entropy model. The latent representation of data is further processed into a plurality of slices of quantized latent representations of data wherein the slices are arranged in an ordinal sequence. A hyperprior processing network generates a hyperprior parameters and a compressed representation of the hyperprior parameters. For each slice, a corresponding compressed representation is generated using a corresponding slice processing network wherein a combination of the compressed representations form a compressed representation of the data.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: December 27, 2022
    Assignee: Google LLC
    Inventors: David Charles Minnen, Saurabh Singh
  • Publication number: 20220353970
    Abstract: The present disclosure relates to current control circuitry for controlling a current through a load, the current control circuitry comprising: amplifier circuitry; reference voltage generator circuitry configured to supply a fixed reference voltage to a first input of the amplifier circuitry; an output stage comprising: a control terminal coupled to an output of the amplifier circuitry; a current input terminal configured to be coupled to the load; a current output terminal; a clock-controlled variable resistance coupled to the current output terminal of the output stage, wherein a resistance of the variable resistance is based on a digital code input to the variable resistance; and a feedback path between the current output terminal of the output stage and a second terminal of the amplifier circuitry for providing a feedback voltage to a second input of the amplifier circuitry.
    Type: Application
    Filed: July 8, 2022
    Publication date: November 3, 2022
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Dave SMITH, Saurabh SINGH, Andrew BUIST, Paulius CEREBIEJUS, Mark J. MCCLOY-STEVENS, Terence A. ORR
  • Publication number: 20220343167
    Abstract: A method of performing federated feature selection for a machine learning model in a federated learning environment includes obtaining, at a first resolution, a global set of selector neural network weights. At a second resolution, the method selects, for a plurality of first data subsets, a first set of features from a feature space by iteratively applying a first selector neural network that is initialized with the global set of selector neural network weights to the first data subset to obtain a first set of selector neural network weights. The first data subsets are divided into a plurality of second data subsets, and, at a third resolution, a second set of features is selected from the feature space.
    Type: Application
    Filed: October 30, 2020
    Publication date: October 27, 2022
    Inventors: Deepa CHAWLA, Gaurav DIXIT, Wenfeng HU, Selim ICKIN, Farnaz MORADI, Erik SANDERS, Saurabh SINGH, Jalil TAGHIA, Konstantinos VANDIKAS
  • Patent number: 11477868
    Abstract: The present disclosure relates to current control circuitry for controlling a current through a load. The current control circuitry comprises amplifier circuitry, reference voltage generator circuitry configured to supply a fixed reference voltage to a first input of the amplifier circuitry and an output stage comprising: a control terminal coupled to an output of the amplifier circuitry; a current input terminal configured to be coupled to the load; and a current output terminal. The current control circuitry further comprises a variable resistance coupled to the current output terminal of the output stage, and a feedback path between the current output terminal of the output stage and a second terminal of the amplifier circuitry for providing a feedback voltage to a second input of the amplifier circuitry.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: October 18, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Dave Smith, Saurabh Singh, Andrew Buist, Paulius Cerebiejus, Mark J. McCloy-Stevens, Terence A. Orr
  • Publication number: 20220283246
    Abstract: A method of detecting a defect in a connecting member of a radio unit in a radio site includes applying an artificial radio traffic load to a first radio unit and at least a second radio unit, such that the radio traffic load experienced by the first and the second radio unit is at a same level, measuring power supplied to the first radio unit via a first connecting member and power supplied to the second radio unit via a second connecting member at an end of each connecting member terminating at a device configured to supply power to the radio units, and determining from the measured power and an expected nominal power loss of the first and the second connecting member if there is power loss in at least one of the first and the second connecting member indicating a defect.
    Type: Application
    Filed: August 9, 2019
    Publication date: September 8, 2022
    Inventors: Lackis ELEFTHERIADIS, Bin SUN, Xiaoyu LAN, Saurabh SINGH, Erik SANDERS, Marios DAOUTIS
  • Patent number: 11411191
    Abstract: Selenium-fullerene heterojunction solar cells and techniques for fabrication thereof are provided. In one aspect, a method of forming a solar cell includes: forming a front contact on a substrate; depositing an n-type semiconducting layer on the front contact, wherein the n-type semiconducting layer comprises a fullerene or fullerene derivative; forming a p-type chalcogen absorber layer on the n-type semiconducting layer; depositing a high workfunction material onto the p-type chalcogen absorber layer, wherein the high workfunction material has a workfunction of greater than about 5.2 electron volts; and forming a back contact on the high workfunction material. Solar cells and other methods for formation thereof are also provided.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 9, 2022
    Assignee: International Business Machines Corporation
    Inventors: Douglas M. Bishop, Yun Seog Lee, Saurabh Singh, Teodor K. Todorov
  • Patent number: 11354822
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for image compression and reconstruction. A request to generate an encoded representation of an input image is received. The encoded representation of the input image is then generated. The encoded representation includes a respective set of binary codes at each iteration. Generating the set of binary codes for the iteration from an initial set of binary includes: for any tiles that have already been masked off during any previous iteration, masking off the tile. For any tiles that have not yet been masked off during any of the previous iterations, a determination is made as to whether a reconstruction error of the tile when reconstructed from binary codes at the previous iterations satisfies an error threshold. When the reconstruction quality satisfies the error threshold, the tile is masked off.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: June 7, 2022
    Assignee: Google LLC
    Inventors: Michele Covell, Damien Vincent, David Charles Minnen, Saurabh Singh, Sung Jin Hwang, Nicholas Johnston, Joel Eric Shor, George Dan Toderici
  • Publication number: 20220138991
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for compressing and decompressing data. In one aspect, a method comprises: processing data using an encoder neural network to generate a latent representation of the data; processing the latent representation of the data using a hyper-encoder neural network to generate a latent representation of an entropy model; generating an entropy encoded representation of the latent representation of the entropy model; generating an entropy encoded representation of the latent representation of the data using the latent representation of the entropy model; and determining a compressed representation of the data from the entropy encoded representations of: (i) the latent representation of the data and (ii) the latent representation of the entropy model used to entropy encode the latent representation of the data.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Inventors: David Charles Minnen, Saurabh Singh, Johannes Balle, Troy Chinen, Sung Jin Hwang, Nicholas Johnston, George Dan Toderici