Abstract: Implementations of the present disclosure generally relates to a transfer chamber coupled to at least one vapor phase epitaxy chamber a plasma oxide removal chamber coupled to the transfer chamber, the plasma oxide removal chamber comprising a lid assembly with a mixing chamber and a gas distributor; a first gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; a second gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; a third gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; and a substrate support with a substrate supporting surface; a lift member disposed in a recess of the substrate supporting surface and coupled through the substrate support to a lift actuator; and a load lock chamber coupled to the transfer chamber.

Abstract: Methods and apparatus for processing a substrate are described herein. Methods for passivating dielectric materials include forming alkyl silyl moieties on exposed surfaces of the dielectric materials. Suitable precursors for forming the alkyl silyl moieties include (trimethylsilyl)pyrrolidine, aminosilanes, and dichlorodimethylsilane, among others. A capping layer may be selectively deposited on source/drain materials after passivation of the dielectric materials. Apparatus for performing the methods described herein include a platform comprising a transfer chamber, a pre-clean chamber, an epitaxial deposition chamber, a passivation chamber, and an atomic layer deposition chamber.

Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.

Abstract: In one embodiment, a susceptor for thermal processing is provided. The susceptor includes an outer rim surrounding and coupled to an inner dish, the outer rim having an inner edge and an outer edge. The susceptor further includes one or more structures for reducing a contacting surface area between a substrate and the susceptor when the substrate is supported by the susceptor. At least one of the one or more structures is coupled to the inner dish proximate the inner edge of the outer rim.

Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.

Abstract: Embodiments disclosed herein generally relate to apparatus and methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a Si:As process has been performed on a substrate, and prior to additional processing. The apparatus includes a purge station including an enclosure, a gas supply coupled to the enclosure, an exhaust pump coupled to the enclosure, a first purge gas port formed in the enclosure, a first channel operatively connected to the gas supply at a first end and to the first purge gas port at a second end, a second purge gas port formed in the enclosure, and a second channel operatively connected to the second purge gas port at a third end and to the exhaust pump at a fourth end. The first channel includes a particle filter, a heater, and a flow controller. The second channel includes a dry scrubber.

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.

Abstract: Methods of sub-10 nm fin formation are disclosed. One method includes patterning a first dielectric layer on a substrate to form one or more projections and a first plurality of spaces, and depositing a first plurality of columns in the first plurality of spaces. The first plurality of columns are separated by a second plurality of spaces. The method also includes depositing a second dielectric layer in the second plurality of spaces to form a plurality of dummy fins, removing the first plurality of columns to form a third plurality of spaces, depositing a second plurality of columns in the third plurality of spaces, removing the one or more projections and the plurality of dummy fins to form a fourth plurality of spaces, and depositing a plurality of fins in the fourth plurality of spaces. The plurality of fins have a width between 5-10 nm.

Abstract: In one embodiment, a susceptor for thermal processing is provided. The susceptor includes an outer rim surrounding and coupled to an inner dish, the outer rim having an inner edge and an outer edge. The susceptor further includes one or more structures for reducing a contacting surface area between a substrate and the susceptor when the substrate is supported by the susceptor. At least one of the one or more structures is coupled to the inner dish proximate the inner edge of the outer rim.

Abstract: Implementations disclosed herein relate to methods for controlling substrate outgassing. In one implementation, the method includes removing oxides from an exposed surface of a substrate in an inductively coupled plasma chamber, forming an epitaxial layer on the exposed surface of the substrate in an epitaxial deposition chamber, and performing an outgassing control of the substrate by subjecting the substrate to a first plasma formed from a first etch precursor in the inductively coupled plasma chamber at a first chamber pressure, wherein the first etch precursor comprises a hydrogen-containing precursor, a chlorine-containing precursor, and an inert gas, and subjecting the substrate to a second plasma formed from a second etch precursor in the inductively coupled plasma chamber at a second chamber pressure that is higher than the first chamber pressure, wherein the second etch precursor comprises a hydrogen-containing precursor and an inert gas.

Abstract: The present disclosure generally relates to a device having a thin, low-defect, fully-relaxed silicon germanium (SiGe) layer, and methods of manufacture thereof. The methods generally include depositing a silicon oxide layer on a silicon layer, patterning the silicon oxide layer, exposing the silicon oxide layer to an etchant to form one or more recesses in the silicon layer and one or more faceted silicon oxide caps, and epitaxially growing a silicon germanium layer in the one or more recesses and over an apex of the one or more faceted silicon oxide caps. The device generally includes a silicon layer having one or more recesses defining one or more vertical extensions, one or more faceted silicon oxide caps on the one or more vertical extensions, and a silicon germanium layer in the one or more recesses and extending over an apex of the one or more faceted silicon oxide caps.

Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. In one embodiment, a method for forming a FinFET device includes removing a portion of each fin of a plurality of fins, and a remaining portion of each fin is recessed from a dielectric surface. The method further includes forming a feature on the remaining portion of each fin, filling gaps formed between adjacent features with a dielectric material, removing the features, and forming a fill material on the remaining portion of each fin. Because the shape of the features is controlled, the shape of the fill material can be controlled.

Abstract: A method of forming a film on a substrate having silicon surfaces and dielectric surfaces includes precleaning the substrate; applying an inhibitor species to the dielectric surfaces; and exposing the substrate to a precursor while maintaining a temperature of less than about 600 degrees Celsius.

Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.

Abstract: The present disclosure generally relates to methods of selectively forming titanium silicides on substrates. The methods are generally utilized in conjunction with contact structure integration schemes. In one embodiment, a titanium silicide material is selectively formed on a substrate as an interfacial layer on a source/drain region. The titanium silicide layer may be formed at a temperature within range of about 400 degrees Celsius to about 500 degrees Celsius.

Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.

Abstract: A method and apparatus for detecting substrate misalignment (i.e., position displacement error) and/or substrate support misalignment. According to certain aspects, a method for detecting a misalignment of an object in a processing system is provided. The method generally includes obtaining a first image of the object, determining first values associated with pixels in at least one region of the first image, calculating at least one of a center of gravity value of the pixels in the at least one region or an average weight of the pixels in the at least one region, and detecting a misalignment of the object based on at least one of the calculated center of gravity or average weight of the pixels in the at least one region.

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.