INTEGRATED SYSTEM AND METHOD FOR SOURCE/DRAIN ENGINEERING
Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.
This application is a continuation of U.S. patent application Ser. No. 15/890,117 filed on Feb. 6, 2018, which is a continuation of U.S. patent application Ser. No. 15/417,496, filed on Jan. 27, 2017, which claims priority to Provisional Patent Application Ser. No. 62/395,765, filed Sep. 16, 2016, and Provisional Patent Application Ser. No. 62/423,082, filed on Nov. 16, 2016, all of which are herein incorporated by reference.
BACKGROUND FieldImplementations of the present disclosure generally relate to the manufacture of semiconductor devices. More specifically, implementations described herein relate to methods for source/drain engineering.
Description of the Related ArtIntegrated circuits are formed in and on silicon and other semiconductor substrates. In the case of single crystal silicon, substrates are made by growing an ingot from a bath of molten silicon, and then sawing the solidified ingot into multiple substrates. An epitaxial silicon layer may then be formed on the monocrystalline silicon substrate to form a defect-free silicon layer that may be doped or undoped. Semiconductor devices, such as transistors, are manufactured from the epitaxial silicon layer. The electrical properties of the formed epitaxial silicon layer will generally be better than the properties of the monocrystalline silicon substrate.
Group IV elements may be advantageous in certain applications for forming silicon-based devices. For example, Group IV elements may serve as a source/drain region in sub-10 nm Fin Field Effect Transistor (FinFET) devices due to the low contact resistance, superior electron mobility and lower operation voltage. However, there are major challenges in preparing a substrate for Group IV source/drain growth. Surfaces of the monocrystalline silicon and the epitaxial silicon layer are susceptible to contamination when exposed to typical fabrication facility ambient conditions, and there might be a few atomic layers of damaged Si from previous process steps. For example, a native oxide layer may form on the monocrystalline silicon surface prior to deposition of the epitaxial layer. Additionally, contaminants present in the ambient environment may deposit on the monocrystalline surface and may come from previous process steps. The presence of a native oxide layer or contaminants on the monocrystalline silicon surface negatively affects the quality of an epitaxial layer subsequently formed on the monocrystalline surface. While present cleaning methods remove some of the native oxides and contaminants from the monocrystalline silicon surface, some contaminants may still remain.
Therefore, there is a need for a method for integrated cleaning a substrate surface and subsequent recessing prior to performing an epitaxial deposition process.
SUMMARYImplementations described herein generally provide a method of processing a workpiece. The method of processing the workpiece includes disposing the workpiece in a processing volume. The workpiece includes a substrate. The substrate includes a source/drain region disposed on the substrate. The method of disposing a workpiece also includes establishing a low pressure processing environment in the processing volume. The method of disposing a workpiece also includes maintaining the low pressure processing environment while delivering a first gas containing to the processing volume, depositing a salt on the workpiece, heating the substrate to greater than 90° C., purging the processing volume with a second inert gas, and recessing the source/drain regions.
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary implementations and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective implementations.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one implementation may be beneficially incorporated in other implementations without further recitation.
DETAILED DESCRIPTIONImplementations of the present disclosure generally relate to methods for forming semiconductor devices. More specifically, methods are described for sub-10 nm cleaning and recessing substrates in preparation for precise Group IV source/drain growth in FinFET devices.
As illustrated in
As shown in
The dielectric material 204, such as a shallow trench isolation (STI) oxide, may comprise one or more of silicon oxide (SiO), silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or other suitable materials that may be used to form a dielectric material. The dielectric material 204 may be deposited by various deposition processes. For example, the dielectric material 204 may be deposited by a chemical vapor deposition (CVD) process, which may be plasma enhanced. The contaminants 206 may include native oxide and dangling silicon bonds saturated with hydrogen such as SiO2 or GeO2. The dummy gate 208 may comprise silicon nitride (SiN). The pre source/drain region 216 may comprise silicon and may further comprise germanium (Ge), carbon (C), boron (B), phosphorous (P), or other materials that may be co-grown, doped and/or associated with silicon materials.
The workpiece, including the device 200, may be placed in an inductively coupled plasma (ICP) plasma reactor chamber. Suitable chambers include the CENTRIS® or MESA® chamber available from Applied Materials, Inc. of Santa Clara, Calif. Chambers available from other manufacturers may also be used to practice implementations described herein. A low pressure processing environment may be established within the chamber at step 50 of
At operation 120 of
At operation 140, while the low pressure environment is maintained, the processing volume and gas lines are purged using a second inert gas mixture. The second inert gas may be a H2/Ar plasma mixture. The second inert gas mixture advantageously removes any residual ammonia (NH3) inside the chamber and gas line providing for a clean surface in preparation for subsequent processing operations.
As shown in
As shown in
The integrated clean and recess process prepares the device 200 for subsequent processing while maintaining a low pressure environment. More specifically, the resulting source/drain region may be free of contaminants and/or defects, may has a desired shape, and may be prepared for subsequent epitaxial growth. The device 200 may undergo additional processing steps within the same cluster tool. Use of a single apparatus containing various processing chambers allows for the various operations of the method 100 of
Thus, methods described for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices are provided. Benefits of this disclosure include precise fin size control in devices, such as sub-10 nm FinFET devices, and increased overall device yield.
While the foregoing is directed to implementations of the present disclosure, other and further implementations of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims
1. A method of processing a workpiece, comprising:
- flowing a first gas mixture into a processing chamber;
- forming a first plasma from the first gas mixture;
- exposing the workpiece to the first plasma, wherein the workpiece comprises: a substrate comprising a source/drain region; and a fin layer extending from a surface of the source/drain region; and
- depositing a salt on one or more surfaces of the source/drain region and the fin layer.
2. The method of claim 1, wherein the first gas mixture comprises NH3 and NF3.
3. The method of claim 1, wherein source/drain region is disposed between a plurality of dielectric material features.
4. The method of claim 1, further comprising:
- flowing a second gas mixture into the processing chamber before flowing the first gas mixture, the second gas mixture comprising hydrogen gas and argon gas;
- forming a second plasma of the second gas mixture; and
- exposing the workpiece to the second plasma before exposing the workpiece to the first plasma.
5. The method of claim 1, wherein the fin layer comprises silicon.
6. The method of claim 1, further comprising:
- heating the workpiece to about 90° C. or more; and
- purging the processing chamber of the first gas mixture by flowing a purge gas mixture thereinto.
7. The method of claim 6, wherein heating the workpiece to about 90° C. or more removes the salt or reaction byproducts of the salt from the one or more surfaces of the source/drain region and the fin layer.
8. The method of claim 7, wherein depositing the salt and removing the salt or reaction byproducts of the salt cleans one or both of a native oxide or contaminates disposed on the one or more surfaces of the source/drain region and the fin layer.
9. The method of claim 8, wherein the workpiece further comprises a dielectric material layer disposed on the fin layer.
10. The method of claim 9, wherein the dielectric material layer is a dummy gate.
11. The method of claim 6, further comprising:
- flowing an etchant gas mixture into the processing chamber;
- forming an etching plasma from the etchant gas mixture; and
- exposing the workpiece to the etching plasma to reduce a width of the fin layer.
12. The method of claim 11, wherein exposing the workpiece to the etching plasma reduces the width of the fin layer by up to about 2 nm.
13. The method of claim 11, wherein the etchant gas mixture comprises chlorine.
14. The method of claim 1, further comprising:
- depositing an Si:As layer on one or more surfaces of the source/drain region.
15. The method of claim 14, further comprising:
- depositing an Si:P layer on one or more surfaces of the source/drain region.
16. A method of processing a substrate, comprising:
- flowing a first processing gas mixture comprising NH3 and NF3 into a processing chamber;
- forming a first plasma from the first processing gas mixture;
- exposing the substrate to the first plasma, wherein the substrate comprises: a source/drain region disposed between a plurality of dielectric material features; and a fin layer extending from a surface of the source/drain region;
- depositing a salt on one or more surfaces of the source/drain region and the fin layer; and
- removing one or both of the salt or reaction byproducts of the salt from the one or more surfaces of the source/drain region and the fin layer, comprising: heating the substrate to 90° C. or more; and purging the processing chamber of the first processing gas mixture by flowing a purging gas thereinto.
17. The method of claim 16, wherein depositing the salt on the one or more surfaces of the source/drain region and the fin layer and removing one or both of the salt or reaction byproducts of the salt and the one or more surfaces of the source/drain region and the fin layer includes removing a native oxide layer formed on the one or more surfaces of the source/drain region and the fin layer.
18. The method of claim 16, further comprising:
- flowing a second processing gas mixture comprising H2 and Cl2 into the processing chamber;
- forming a second plasma from the second processing gas mixture; and
- exposing the substrate to the second plasma.
19. The method of claim 18, wherein exposing the substrate to the second plasma removes a material thickness of up to about 2 nm from the one or more surfaces of the source/drain region and the fin layer.
20. The method of claim 19, further comprising:
- depositing an Si:P layer on one or more surfaces of the source/drain region.
21. The method of claim 5, wherein the fin layer further comprises at least one of germanium, carbon, boron, and phosphorous.
Type: Application
Filed: Oct 1, 2018
Publication Date: Jan 31, 2019
Inventors: Chun YAN (San Jose, CA), Xinyu BAO (Fremont, CA), Melitta Manyin HON (San Jose, CA), Hua CHUNG (San Jose, CA), Schubert S. CHU (San Francisco, CA)
Application Number: 16/148,430