Patents by Inventor Scott Balster
Scott Balster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10937905Abstract: A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.Type: GrantFiled: May 23, 2014Date of Patent: March 2, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Philip L. Hower, Sameer P. Pendharkar, John Lin, Guru Mathur, Scott Balster, Victor Sinow
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Publication number: 20150340496Abstract: A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.Type: ApplicationFiled: May 23, 2014Publication date: November 26, 2015Applicant: Texas Instruments IncorporatedInventors: YONGXI ZHANG, PHILIP L. HOWER, SAMEER P. PENDHARKAR, JOHN LIN, GURU MATHUR, SCOTT BALSTER, VICTOR SINOW
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Patent number: 8703568Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: GrantFiled: January 26, 2012Date of Patent: April 22, 2014Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
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Patent number: 8450179Abstract: A method for fabricating a semiconductor device having a first and second bipolar devices of the same dopant type includes: depositing a dielectric layer over a semiconductor layer, depositing a gate conductor layer over the dielectric layer, defining base regions of both bipolar devices, removing the gate conductor layer and dielectric layer in the base regions, depositing a base layer on the gate conductor layer and on the exposed semiconductor layer in the base regions, depositing an insulating layer over the base layer, forming a photoresist layer and defining emitter regions of both bipolar devices, removing the photoresist layer in the emitter regions thereby forming two emitter windows, masking the emitter window of the first bipolar device and exposing the base layer in the base region of the second bipolar device to an additional emitter implant through the associated emitter window.Type: GrantFiled: February 2, 2007Date of Patent: May 28, 2013Assignee: Texas Instruments Deutschland GmbHInventors: Badih El-Kareh, Hiroshi Yasuda, Scott Balster
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Publication number: 20120164802Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: ApplicationFiled: January 26, 2012Publication date: June 28, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
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Patent number: 8129246Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: GrantFiled: January 13, 2011Date of Patent: March 6, 2012Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
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Patent number: 8012842Abstract: An integrated semiconductor structure that has first and second bipolar transistor structures. The first bipolar transistor structure has a doped tank region in contact with a doped tank region located underneath a contacting sinker. The second bipolar transistor structure has a doped buried region that is the same dopant type as its doped tank region. A method for fabricating an integrated semiconductor structure in a bulk semiconductor wafer. A first patterned photomask is used to form a doped buried region and a doped tank region within the first bipolar transistor structure. A second patterned photomask is used to form a doped buried region and a doped tank region within the second bipolar transistor, plus a doped buried region and a doped tank region underneath a contacting sinker adjacent to the first bipolar transistor.Type: GrantFiled: June 12, 2008Date of Patent: September 6, 2011Assignee: Texas Instruments IncorporatedInventors: Scott Balster, Badih El-Kareh, Hiroshi Yasuda
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Publication number: 20110111553Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: ApplicationFiled: January 13, 2011Publication date: May 12, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
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Patent number: 7883977Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: GrantFiled: January 20, 2009Date of Patent: February 8, 2011Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
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Patent number: 7736986Abstract: An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide, a second capacitor film (48) and a first dielectric (26) sandwiched between the first capacitor film (46) and second capacitor film (48). A second dielectric (34) and a third capacitor film (50) are provided. The second dielectric (34) is sandwiched between the second capacitor film (48) and third capacitor film (50). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer (20) to form the first capacitor film (46); applying a first dielectric (26); applying a first metallization layer (28) to form the second capacitor film (48); applying a second dielectric (34); and applying a second metallization layer (44) to form the third capacitor film (50).Type: GrantFiled: April 26, 2007Date of Patent: June 15, 2010Assignee: Texas Instruments IncorporatedInventors: Christoph Dirnecker, Jeffrey Babcock, Scott Balster
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Patent number: 7655523Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: GrantFiled: October 30, 2007Date of Patent: February 2, 2010Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
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Publication number: 20090130805Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: ApplicationFiled: January 20, 2009Publication date: May 21, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
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Publication number: 20090127630Abstract: An integrated semiconductor structure and a method for fabricating an integrated semiconductor structure in a bulk semiconductor wafer.Type: ApplicationFiled: June 12, 2008Publication date: May 21, 2009Applicant: Texas Instruments IncorporatedInventors: Scott Balster, Badih El-Kareh, Hiroshi Yasuda
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Patent number: 7501324Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: GrantFiled: April 27, 2006Date of Patent: March 10, 2009Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
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Patent number: 7498639Abstract: An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor circuit, which comprise active window structures for base and/or emitter windows. The integrated BiCMOS semiconductor circuit has zones where silicon is left to form dummy moat areas which do not include electrically active components, and has isolation trenches to separate the active moat areas from each other and from the dummy moat areas. The dummy moat areas comprise dummy window structures having geometrical dimensions and shapes similar to those of the active window structures for the base and/or emitter windows.Type: GrantFiled: September 23, 2005Date of Patent: March 3, 2009Assignee: Texas Instruments IncorporatedInventors: Philipp Steinmann, Scott Balster, Badih El-Kareh, Thomas Scharnagl, Michael Schmitt
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Publication number: 20080265368Abstract: An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide (poly), a second capacitor film (48) and a first dielectric (26) sandwiched between the first capacitor film (46) and second capacitor film (48). A second dielectric (34) and a third capacitor film (50) are provided. The second dielectric (34) is sandwiched between the second capacitor film (48) and third capacitor film (50). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer (20) to form the first capacitor film (46); applying a first dielectric (26); applying a first metallization layer (28) to form the second capacitor film (48); applying a second dielectric (34); and applying a second metallization layer (34) to form the third capacitor film (50).Type: ApplicationFiled: April 26, 2007Publication date: October 30, 2008Applicant: Texas Instruments IncorporatedInventors: Christoph Dirnecker, Jeffrey Babcock, Scott Balster
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Patent number: 7422972Abstract: An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements (70) in close proximity to the programmable structure (60) to heat the programmable structure (60) during programming.Type: GrantFiled: July 15, 2005Date of Patent: September 9, 2008Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Angelo Pinto, Gregory E. Howard, Philipp Steinmann, Scott Balster
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Publication number: 20080132012Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).Type: ApplicationFiled: October 30, 2007Publication date: June 5, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
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Publication number: 20070207585Abstract: A method of fabricating a BiCMOS device comprising a first bipolar device and a second bipolar device being of the same dopant type and a BiCMOS device comprising a first bipolar device and a second bipolar device being of the same dopant type A method for fabricating a BICMOS device comprising a first bipolar device and a second bipolar device being of the same dopant type comprises the steps of depositing a dielectric layer (24) over a semiconductor layer (14), depositing a gate conductor layer (26) over the dielectric layer (24), defining base regions (28, 30) of the first and second bipolar devices; removing the gate conductor layer (26) and the dielectric layer (24) in the base regions (28, 30) of the first and second bipolar devices, depositing a base layer (32) on the gate conductor layer (26) and on the exposed semiconductor layer (14) in the base regions (28, 30) of the first and second bipolar devices depositing an insulating layer (36) over said base layer (32), forming a photoresist layer (38) anType: ApplicationFiled: February 2, 2007Publication date: September 6, 2007Applicant: TEXAS INSTRUMENTS INCOPRORATEDInventors: Badih El-Kareh, Hiroshi Yasuda, Scott Balster
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Patent number: 7227241Abstract: An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide (poly), a second capacitor film (48) and a first dielectric (26) sandwiched between the first capacitor film (46) and second capacitor film (48). A second dielectric (34) and a third capacitor film (50) are provided. The second dielectric (34) is sandwiched between the second capacitor film (48) and third capacitor film (50). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer (20) to form the first capacitor film (46); applying a first dielectric (26); applying a first metallization layer (28) to form the second capacitor film (48); applying a second dielectric (34); and applying a second metallization layer (34) to form the third capacitor film (50).Type: GrantFiled: May 20, 2004Date of Patent: June 5, 2007Assignee: Texas Instruments IncorporatedInventors: Christoph Dirnecker, Jeffrey Babcock, Scott Balster