Patents by Inventor Scott Beasor

Scott Beasor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190273148
    Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 5, 2019
    Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
  • Patent number: 10403742
    Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 3, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
  • Publication number: 20190259668
    Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.
    Type: Application
    Filed: February 20, 2018
    Publication date: August 22, 2019
    Inventors: Chang Seo Park, Haiting Wang, Shimpei Yamaguchi, Junsic Hong, Yong Mo Yang, Scott Beasor
  • Patent number: 10373877
    Abstract: One illustrative method disclosed herein includes forming a plurality of transistors on a semiconductor substrate, wherein each of the transistors comprise source/drain epitaxial semiconductor material in the source/drain regions, a contact etch stop layer (CESL) positioned above the source/drain epitaxial semiconductor material and an insulating material positioned above the contact etch stop layer, and forming a plurality of contact isolation cavities by performing at least one etching process sequence, wherein the etching process sequence is adapted to sequentially remove the insulating material, the CESL and the source/drain epitaxial semiconductor material, and forming a contact isolation structure in each of the contact isolation cavities.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: August 6, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Haiting Wang, Hong Yu, Hui Zang, Wei Zhao, Yue Zhong, Guowei Xu, Laertis Economikos, Jerome Ciavatti, Scott Beasor
  • Patent number: 10361289
    Abstract: A method of thermally oxidizing a Si fin to form an oxide layer over the Si fin and then forming an ALD oxide layer over the oxide layer and resulting device are provided. Embodiments include forming a plurality of Si fins on a Si substrate; forming a dielectric layer over the plurality of Si fins and the Si substrate; recessing the dielectric layer, exposing a top portion of the plurality of Si fins; thermally oxidizing surface of the top portion of the plurality of Si fins, an oxide layer formed; and forming an ALD oxide layer over the oxide layer.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Zhao, Shahab Siddiqui, Haiting Wang, Ting-Hsiang Hung, Yiheng Xu, Beth Baumert, Jinping Liu, Scott Beasor, Yue Zhong, Shesh Mani Pandey
  • Publication number: 20190221483
    Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si). The silicon germanium layers include etch-selective high-germanium content silicon germanium layers and low-germanium content silicon germanium layers. Single work function metal PFET and NFET devices can be formed on the same substrate by incorporating the low-germanium content silicon germanium layers into the channel region within p-type device regions, whereas both the high-germanium content silicon germanium layers and the low-germanium content silicon germanium layers are removed from within n-type device regions.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 18, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: George MULFINGER, Scott BEASOR, Timothy MCARDLE
  • Publication number: 20190214308
    Abstract: Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 11, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yiheng Xu, Haiting Wang, Qun Gao, Scott Beasor, Kyung Bum Koo, Ankur Arya
  • Patent number: 10326002
    Abstract: Methods of forming self-aligned gate contacts and cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include self-aligned gate contacts and cross-coupling contacts. A sidewall spacer is formed at a sidewall of a gate structure and an epitaxial semiconductor layer is formed adjacent to the sidewall spacer. After forming the epitaxial semiconductor layer, the sidewall spacer is recessed with a first etching process. After recessing the spacer, the gate structure is recessed with a second etching process. After recessing the gate structure, a cross-coupling contact is formed that connects the gate structure with the epitaxial semiconductor layer.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 18, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Ruilong Xie, Scott Beasor, Zhenyu Hu
  • Publication number: 20190164898
    Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. An upper portion of the isolation architecture is removed and replaced with a high-k, etch-selective spacer layer adapted to resist degradation during an etch to open the source/drain contact locations. The high-k spacer layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate and overlapping a sidewall of the isolation layer, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.
    Type: Application
    Filed: November 28, 2017
    Publication date: May 30, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui ZANG, Guowei XU, Scott BEASOR, Ruilong Xie
  • Publication number: 20190109197
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.
    Type: Application
    Filed: October 9, 2017
    Publication date: April 11, 2019
    Inventors: Haiting WANG, Wei ZHAO, Hui ZANG, Hong YU, Zhenyu HU, Scott BEASOR, Erik GEISS, Jerome CIAVATTI, Jae Gon LEE
  • Publication number: 20190097019
    Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.
    Type: Application
    Filed: September 22, 2017
    Publication date: March 28, 2019
    Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
  • Publication number: 20180277427
    Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.
    Type: Application
    Filed: May 24, 2018
    Publication date: September 27, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Viraj SARDESAI, Suraj K. PATIL, Scott BEASOR, Vimal Kumar KAMINENI
  • Publication number: 20180233505
    Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in a PFET region; a pair of Si fins formed in a NFET region; epitaxial S/D regions formed on ends of the Si fins; a replacement metal gate formed over the Si fins in the PFET and NFET regions; metal silicide trenches formed over the epitaxial S/D regions in the PFET and NEFT regions; a metal layer formed over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region, wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view.
    Type: Application
    Filed: September 28, 2017
    Publication date: August 16, 2018
    Inventors: George R. MULFINGER, Lakshmanan H. VANAMURTHY, Scott BEASOR, Timothy J. MCARDLE, Judson R. HOLT, Hao ZHANG
  • Patent number: 10049944
    Abstract: A method for integrating nanostructures in finFET processing and a related device are provided. Embodiments include forming fins in a Si substrate in first and second device regions; forming STI regions in spaces between fins; forming a first hardmask over the fins and STI regions; removing a portion of the first hardmask over the first device region to expose upper surfaces of the fins and STI regions in the first device region; recessing an upper portion of the fins; forming first devices over the recessed fins; forming a second hardmask over the fins and STI regions; removing a portion of the second hardmask over the second device region to expose upper surfaces of the fins and STI regions; recessing an upper portion of the fins; and forming second devices, different from the first devices, over the recessed fins, wherein the first and/or second devices include nanowire or nanosheet devices.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: August 14, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Scott Beasor, Jeremy A. Wahl
  • Patent number: 10043708
    Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: August 7, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Viraj Sardesai, Suraj K. Patil, Scott Beasor, Vimal Kumar Kamineni
  • Patent number: 9984933
    Abstract: A hardmask is patterned on a first material to leave hardmask elements. The first material is patterned into fins through the hardmask. A layer of silicon is formed on the hardmask elements and the fins in processing that forms the layer of silicon thicker on the hardmask elements relative to the fins. An isolation material is formed on the layer of silicon to leave the isolation material filling spaces between the fins. The isolation material and the layer of silicon are annealed to consume relatively thinner portions of the layer of silicon and leave the layer of silicon on the hardmask elements as silicon elements. A chemical mechanical polishing (CMP) is performed on the isolation material to make the isolation material planar with the silicon elements. A first etching agent removes the silicon elements on the hardmask elements, and a second chemical agent removes the hardmask elements.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: May 29, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yiheng Xu, Haiting Wang, Wei Zhao, Todd B. Abrams, Jiehui Shu, Jinping Liu, Scott Beasor
  • Publication number: 20180130703
    Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.
    Type: Application
    Filed: November 9, 2016
    Publication date: May 10, 2018
    Inventors: Viraj SARDESAI, Suraj K. PATIL, Scott BEASOR, Vimal Kumar KAMINENI
  • Publication number: 20180096899
    Abstract: A method for integrating nanostructures in finFET processing and a related device are provided. Embodiments include forming fins in a Si substrate in first and second device regions; forming STI regions in spaces between fins; forming a first hardmask over the fins and STI regions; removing a portion of the first hardmask over the first device region to expose upper surfaces of the fins and STI regions in the first device region; recessing an upper portion of the fins; forming first devices over the recessed fins; forming a second hardmask over the fins and STI regions; removing a portion of the second hardmask over the second device region to expose upper surfaces of the fins and STI regions; recessing an upper portion of the fins; and forming second devices, different from the first devices, over the recessed fins, wherein the first and/or second devices include nanowire or nanosheet devices.
    Type: Application
    Filed: October 5, 2016
    Publication date: April 5, 2018
    Inventors: Scott BEASOR, Jeremy A. WAHL
  • Publication number: 20170338180
    Abstract: A method for producing semiconductor devices including an electrical fuse (e-fuse) and the resulting device are provided. Embodiments include forming a gate electrode (PC); forming at least one gate contact (CB) over the PC; forming at least one source/drain contact (CA); and forming an e-fuse including a resistor metal (RM) between at least one CB and an equal number of CAs to dissipate heat generated by the PC.
    Type: Application
    Filed: May 18, 2016
    Publication date: November 23, 2017
    Inventors: Scott BEASOR, Jagar SINGH
  • Patent number: 9812453
    Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include forming a Si fin in a PFET region and a pair of Si fins in a NFET region; forming epitaxial S/D regions; forming a spacer over the S/D region in the PFET region; forming a sacrificial cap over the S/D regions in the NFET region, merging the pair of Si fins; removing the spacer from the S/D region in the PFET region; forming silicide trenches over the S/D regions in the PFET and NEFT regions; implanting dopant into the S/D region in the PFET region while the sacrificial cap protects the S/D regions in the NFET region; removing the sacrificial cap; and forming a metal layer over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: November 7, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George R. Mulfinger, Lakshmanan H. Vanamurthy, Scott Beasor, Timothy J. McArdle, Judson R. Holt, Hao Zhang