Patents by Inventor Scott Beasor
Scott Beasor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190393321Abstract: Various processes form different structures including exemplary apparatuses that include (among other components) a first layer having channel regions, source/drain structures in the first layer on opposite sides of the channel regions, a gate insulator on the channel region, and a gate stack on the gate insulator. The gate stack can include a gate conductor, and a stack insulator or a gate contact on the gate conductor. The gate stack has lower sidewalls adjacent to the source/drain structures and upper sidewalls distal to the source/drain structures. Further, lower spacers are between the source/drain contacts and the lower sidewalls of the gate stack; and upper spacers between the source/drain contacts and the upper sidewalls of the gate stack. In some structures, the upper spacers can partially overlap the lower spacers.Type: ApplicationFiled: June 21, 2018Publication date: December 26, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Guowei Xu, Hui Zang, Haiting Wang, Scott Beasor
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Publication number: 20190378763Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile.Type: ApplicationFiled: June 11, 2018Publication date: December 12, 2019Inventors: Haiting WANG, Ruilong XIE, Shesh Mani PANDEY, Hui ZANG, Garo Jacques DERDERIAN, Scott BEASOR
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Publication number: 20190363053Abstract: One illustrative example of an overlay mark disclosed herein includes four quadrants (I-IV). Each quadrant of the mark contains an inner periodic structure and an outer periodic structure. Each of the outer periodic structures includes a plurality of outer features. Each of the inner periodic structures includes a plurality of first inner groups, each of the first inner groups having a plurality of first inner features, each first inner group being oriented such that there is an end-to-end spacing relationship between each first inner group and a selected one of the outer features.Type: ApplicationFiled: May 22, 2018Publication date: November 28, 2019Inventors: Wei Zhao, Minghao Tang, Rui Chen, Dongyue Yang, Haiting Wang, Erik Geiss, Scott Beasor
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Publication number: 20190355838Abstract: A method for producing a finFET to prevent gate contact and trench silicide (TS) electrical shorts. Embodiments include forming a finFET over a substrate, the finFET comprising an epi S/D region formed at sides of a gate; forming an ?-Si layer in a recess over the epi S/D; forming an oxide layer over the ?-Si layer; forming a non-TS isolation opening over the substrate; forming a low dielectric constant layer in the non-TS isolation opening; removing the oxide layer and ?-Si layer; forming an opening over the gate and an opening over the epi S/D region; and forming a gate contact in the opening over the gate and an epi S/D contact over the opening over the epi S/D region.Type: ApplicationFiled: May 15, 2018Publication date: November 21, 2019Inventors: Hui ZANG, Ruilong XIE, Scott BEASOR
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Publication number: 20190348517Abstract: The present disclosure relates to semiconductor structures and, more particularly, to chamfered replacement gate structures and methods of manufacture. The structure includes: a recessed gate dielectric material in a trench structure; a plurality of recessed workfunction materials within the trench structure on the recessed gate dielectric material; a plurality of additional workfunction materials within the trench structure and located above the recessed gate dielectric material and the plurality of recessed workfunction materials; a gate metal within the trench structure and over the plurality of additional workfunction materials, the gate metal and the plurality of additional workfunction materials having a planar surface below a top surface of the trench structure; and a capping material over the gate metal and the plurality of additional workfunction materials.Type: ApplicationFiled: May 8, 2018Publication date: November 14, 2019Inventors: Haiting WANG, Rongtao LU, Chih-Chiang CHANG, Guowei XU, Hui ZANG, Scott BEASOR, Ruilong XIE
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Patent number: 10475890Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.Type: GrantFiled: October 9, 2017Date of Patent: November 12, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Haiting Wang, Wei Zhao, Hui Zang, Hong Yu, Zhenyu Hu, Scott Beasor, Erik Geiss, Jerome Ciavatti, Jae Gon Lee
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Publication number: 20190273148Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.Type: ApplicationFiled: May 17, 2019Publication date: September 5, 2019Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
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Patent number: 10403742Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.Type: GrantFiled: September 22, 2017Date of Patent: September 3, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
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Publication number: 20190259668Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.Type: ApplicationFiled: February 20, 2018Publication date: August 22, 2019Inventors: Chang Seo Park, Haiting Wang, Shimpei Yamaguchi, Junsic Hong, Yong Mo Yang, Scott Beasor
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Patent number: 10373877Abstract: One illustrative method disclosed herein includes forming a plurality of transistors on a semiconductor substrate, wherein each of the transistors comprise source/drain epitaxial semiconductor material in the source/drain regions, a contact etch stop layer (CESL) positioned above the source/drain epitaxial semiconductor material and an insulating material positioned above the contact etch stop layer, and forming a plurality of contact isolation cavities by performing at least one etching process sequence, wherein the etching process sequence is adapted to sequentially remove the insulating material, the CESL and the source/drain epitaxial semiconductor material, and forming a contact isolation structure in each of the contact isolation cavities.Type: GrantFiled: May 22, 2018Date of Patent: August 6, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Haiting Wang, Hong Yu, Hui Zang, Wei Zhao, Yue Zhong, Guowei Xu, Laertis Economikos, Jerome Ciavatti, Scott Beasor
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Patent number: 10361289Abstract: A method of thermally oxidizing a Si fin to form an oxide layer over the Si fin and then forming an ALD oxide layer over the oxide layer and resulting device are provided. Embodiments include forming a plurality of Si fins on a Si substrate; forming a dielectric layer over the plurality of Si fins and the Si substrate; recessing the dielectric layer, exposing a top portion of the plurality of Si fins; thermally oxidizing surface of the top portion of the plurality of Si fins, an oxide layer formed; and forming an ALD oxide layer over the oxide layer.Type: GrantFiled: March 22, 2018Date of Patent: July 23, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Wei Zhao, Shahab Siddiqui, Haiting Wang, Ting-Hsiang Hung, Yiheng Xu, Beth Baumert, Jinping Liu, Scott Beasor, Yue Zhong, Shesh Mani Pandey
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Publication number: 20190221483Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si). The silicon germanium layers include etch-selective high-germanium content silicon germanium layers and low-germanium content silicon germanium layers. Single work function metal PFET and NFET devices can be formed on the same substrate by incorporating the low-germanium content silicon germanium layers into the channel region within p-type device regions, whereas both the high-germanium content silicon germanium layers and the low-germanium content silicon germanium layers are removed from within n-type device regions.Type: ApplicationFiled: January 12, 2018Publication date: July 18, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: George MULFINGER, Scott BEASOR, Timothy MCARDLE
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Publication number: 20190214308Abstract: Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Yiheng Xu, Haiting Wang, Qun Gao, Scott Beasor, Kyung Bum Koo, Ankur Arya
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Patent number: 10326002Abstract: Methods of forming self-aligned gate contacts and cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include self-aligned gate contacts and cross-coupling contacts. A sidewall spacer is formed at a sidewall of a gate structure and an epitaxial semiconductor layer is formed adjacent to the sidewall spacer. After forming the epitaxial semiconductor layer, the sidewall spacer is recessed with a first etching process. After recessing the spacer, the gate structure is recessed with a second etching process. After recessing the gate structure, a cross-coupling contact is formed that connects the gate structure with the epitaxial semiconductor layer.Type: GrantFiled: June 11, 2018Date of Patent: June 18, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Hui Zang, Ruilong Xie, Scott Beasor, Zhenyu Hu
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Publication number: 20190164898Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. An upper portion of the isolation architecture is removed and replaced with a high-k, etch-selective spacer layer adapted to resist degradation during an etch to open the source/drain contact locations. The high-k spacer layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate and overlapping a sidewall of the isolation layer, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.Type: ApplicationFiled: November 28, 2017Publication date: May 30, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Hui ZANG, Guowei XU, Scott BEASOR, Ruilong Xie
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Publication number: 20190109197Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.Type: ApplicationFiled: October 9, 2017Publication date: April 11, 2019Inventors: Haiting WANG, Wei ZHAO, Hui ZANG, Hong YU, Zhenyu HU, Scott BEASOR, Erik GEISS, Jerome CIAVATTI, Jae Gon LEE
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Publication number: 20190097019Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.Type: ApplicationFiled: September 22, 2017Publication date: March 28, 2019Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
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Publication number: 20180277427Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.Type: ApplicationFiled: May 24, 2018Publication date: September 27, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: Viraj SARDESAI, Suraj K. PATIL, Scott BEASOR, Vimal Kumar KAMINENI
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Publication number: 20180233505Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in a PFET region; a pair of Si fins formed in a NFET region; epitaxial S/D regions formed on ends of the Si fins; a replacement metal gate formed over the Si fins in the PFET and NFET regions; metal silicide trenches formed over the epitaxial S/D regions in the PFET and NEFT regions; a metal layer formed over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region, wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view.Type: ApplicationFiled: September 28, 2017Publication date: August 16, 2018Inventors: George R. MULFINGER, Lakshmanan H. VANAMURTHY, Scott BEASOR, Timothy J. MCARDLE, Judson R. HOLT, Hao ZHANG
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Patent number: 10049944Abstract: A method for integrating nanostructures in finFET processing and a related device are provided. Embodiments include forming fins in a Si substrate in first and second device regions; forming STI regions in spaces between fins; forming a first hardmask over the fins and STI regions; removing a portion of the first hardmask over the first device region to expose upper surfaces of the fins and STI regions in the first device region; recessing an upper portion of the fins; forming first devices over the recessed fins; forming a second hardmask over the fins and STI regions; removing a portion of the second hardmask over the second device region to expose upper surfaces of the fins and STI regions; recessing an upper portion of the fins; and forming second devices, different from the first devices, over the recessed fins, wherein the first and/or second devices include nanowire or nanosheet devices.Type: GrantFiled: October 5, 2016Date of Patent: August 14, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Scott Beasor, Jeremy A. Wahl