Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.

Abstract: A hardmask is patterned on a first material to leave hardmask elements. The first material is patterned into fins through the hardmask. A layer of silicon is formed on the hardmask elements and the fins in processing that forms the layer of silicon thicker on the hardmask elements relative to the fins. An isolation material is formed on the layer of silicon to leave the isolation material filling spaces between the fins. The isolation material and the layer of silicon are annealed to consume relatively thinner portions of the layer of silicon and leave the layer of silicon on the hardmask elements as silicon elements. A chemical mechanical polishing (CMP) is performed on the isolation material to make the isolation material planar with the silicon elements. A first etching agent removes the silicon elements on the hardmask elements, and a second chemical agent removes the hardmask elements.

Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.

Abstract: A method for integrating nanostructures in finFET processing and a related device are provided. Embodiments include forming fins in a Si substrate in first and second device regions; forming STI regions in spaces between fins; forming a first hardmask over the fins and STI regions; removing a portion of the first hardmask over the first device region to expose upper surfaces of the fins and STI regions in the first device region; recessing an upper portion of the fins; forming first devices over the recessed fins; forming a second hardmask over the fins and STI regions; removing a portion of the second hardmask over the second device region to expose upper surfaces of the fins and STI regions; recessing an upper portion of the fins; and forming second devices, different from the first devices, over the recessed fins, wherein the first and/or second devices include nanowire or nanosheet devices.

Abstract: A method for producing semiconductor devices including an electrical fuse (e-fuse) and the resulting device are provided. Embodiments include forming a gate electrode (PC); forming at least one gate contact (CB) over the PC; forming at least one source/drain contact (CA); and forming an e-fuse including a resistor metal (RM) between at least one CB and an equal number of CAs to dissipate heat generated by the PC.

Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include forming a Si fin in a PFET region and a pair of Si fins in a NFET region; forming epitaxial S/D regions; forming a spacer over the S/D region in the PFET region; forming a sacrificial cap over the S/D regions in the NFET region, merging the pair of Si fins; removing the spacer from the S/D region in the PFET region; forming silicide trenches over the S/D regions in the PFET and NEFT regions; implanting dopant into the S/D region in the PFET region while the sacrificial cap protects the S/D regions in the NFET region; removing the sacrificial cap; and forming a metal layer over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region.

Abstract: A semiconductor structure includes a semiconductor substrate, semiconductor device(s) on the substrate, and metal resistor layer(s) above the semiconductor device(s), each metal resistor layer acting as a first plate for a MIM capacitor. The structure further includes a layer of insulator material above the first plate, and metal conductor layer(s) above the insulator layer, each metal conductor layer acting as a second plate for a MIM capacitor. Fabricating the MIM capacitor uses metal and insulator used in creating electrical connections to the semiconductor device(s), saving two masks typically used to fabricate a MIM capacitor.

Abstract: P-type metal-oxide semiconductor field-effect transistors (pMOSFET's), semiconductor devices comprising the pMOSFET's, and methods of forming pMOSFET's are provided. The pMOSFET's include a silicon-germanium (SiGe) film that has a lower interface in contact with a semiconductor substrate and an upper surface, and the SiGe film has a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film.

Abstract: A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an ILD layer of dielectric material overlying a semiconductor substrate that includes a device region to form first contact vias that expose active areas of the device region. The ILD layer is etched to form second contact vias that correspondingly expose a gate that is disposed in the device region and a patterned resistive metal-containing layer that is disposed in the ILD layer adjacent to the device region. The first contact vias and the second contact vias are filled with an electrically-conductive material to form first contacts that are in electrical communication with the active areas and second contacts that include a gate contact and a metal resistor contact that are in electrical communication with the gate and the patterned resistive metal-containing layer, respectively.

Abstract: P-type metal-oxide semiconductor field-effect transistors (pMOSFET's), semiconductor devices comprising the pMOSFET's, and methods of forming pMOSFET's are provided. The pMOSFET's include a silicon-germanium (SiGe) film that has a lower interface in contact with a semiconductor substrate and an upper surface, and the SiGe film has a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an ILD layer of dielectric material overlying a semiconductor substrate that includes a device region to form first contact vias that expose active areas of the device region. The ILD layer is etched to form second contact vias that correspondingly expose a gate that is disposed in the device region and a patterned resistive metal-containing layer that is disposed in the ILD layer adjacent to the device region. The first contact vias and the second contact vias are filled with an electrically-conductive material to form first contacts that are in electrical communication with the active areas and second contacts that include a gate contact and a metal resistor contact that are in electrical communication with the gate and the patterned resistive metal-containing layer, respectively.

Abstract: A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.

Abstract: A method of silicide formation in a semiconductor fabrication process is disclosed. An active area (RX) mask is used to form an active silicon area, and is then reused to form a trench transfer (TT) area. A trench block (TB) mask is logically ANDed with the active area (RX) mask to form a trench silicide (TS) region.

Abstract: A method of silicide formation in a semiconductor fabrication process is disclosed. An active area (RX) mask is used to form an active silicon area, and is then reused to form a trench transfer (TT) area. A trench block (TB) mask is logically ANDed with the active area (RX) mask to form a trench silicide (TS) region.

Abstract: Methods of manufacturing semiconductor integrated circuits having a compressive nitride layer are disclosed. In one example, a method of fabricating an integrated circuit includes depositing an aluminum layer over a semiconductor substrate, depositing a tensile silicon nitride layer or a neutral silicon nitride layer over the aluminum layer, and depositing a compressive silicon nitride layer over the tensile silicon nitride layer or the neutral silicon nitride layer. The compressive silicon nitride layer is deposited at a thickness that is at least about twice a thickness of the tensile silicon nitride layer or the neutral silicon nitride layer. Further, there is no delamination present at an interface between the aluminum layer and the tensile silicon nitride layer or the neutral silicon nitride layer, or at an interface between tensile silicon nitride layer or the neutral silicon nitride layer and the compressive nitride layer.