Abstract: Various embodiments of a method and apparatus for simulating temperature characteristics of a diode are disclosed. The output of a diode simulator may not depend upon its ambient temperature. Therefore, it may be used to calibrate a temperature measurement unit at any ambient temperature within its operational range regardless of the temperature to which the temperature measurement unit is to be calibrated. Even if the ambient temperature of the facility in which the calibration is performed varies during the calibration procedure, the output of the diode simulator may remain constant. These characteristics of the diode simulator may allow for calibration of a temperature measurement unit in significantly less time than by using prior art methods, which include the requirement to tightly control the temperature of one or more system components.

Abstract: In one set of embodiments the invention comprises a highly accurate, low-power, compact size DAC utilizing charge redistribution techniques. Two complementary conversions may be performed and added together to form a final DAC output voltage by performing charge redistribution a first time, and again a second time in a complementary fashion, followed by a summing of the two charge distributions, in effect canceling the odd order capacitor mismatch errors. By canceling all odd order mismatch errors the accuracy of the DAC may become a function of the square of the mismatch of the two capacitors, resulting in greatly increased accuracy. When performing the complementary conversions for multiple bits, the sequence in which each of the two capacitors is charged may be determined to minimize the even-order errors, especially second-order errors.

Abstract: A method of processing content includes storing verification information corresponding to certified content at a first computer and receiving a verification request corresponding to content from a second computer. The method also includes determining verification information for the content corresponding to the verification request and comparing the determined verification information with the stored verification information.

Abstract: The present invention teaches a variety of transconductance circuits formed having a class AB transconductor amplifier coupled in parallel with at least one concave compensation circuit. When the transconductance circuit has only one concave compensation circuit, the concave compensation circuit is designed with no offset so that the concave transconductance gain of the compensation circuit compensates for the convex transconductance gain of the class AB amplifier thereby providing a more linear transconductance circuit. When the transconductance circuit includes multiple concave compensation circuits, they each are designed with an offset chosen such that the combination of the individual concave transfer functions achieve a more linear transconductance circuit.

Abstract: A self-calibrating pulse compression system which is able to optimally compress a chirped waveform notwithstanding variations in the chirped spectrum due to changes in transmitter characteristics or other factors. In a most general sense, the inventive pulse compression system includes a first circuit (12, 14) for providing a first waveform, a second circuit (16, 30, 32) for sampling the first waveform at predetermined time intervals to provide a plurality of calibration samples, a third circuit (30) for storing the calibration samples; and fourth circuit (16, 28, 30) for multiplying a second waveform by the stored calibration samples. In a specific implementation, the first circuit of the self-calibrating pulse compression system includes an impatt chirp transmitter (12). The output of the transmitter (12) is fed to an antenna (18) and to a first switch (22) by a circulator (20). The switch (22) is controlled by a timing circuit (16) which may be implemented with software in a host computer.

Abstract: A digitally controlled oscillator (100) having a first oscillator circuit (108) for providing an oscillator signal F.sub.o of a defined frequency and a digital divider (110) for dividing the oscillator signal F.sub.o by a selectable number controlled by a digital word for providing a clock signal F.sub.clk. A second oscillator circuit (104) receives the clock signal F.sub.clk and provides a low frequency signal F.sub.c. The second oscillator circuit includes a digitally controlled resonator element (112) for determining the frequency of the low frequency signal and has a center frequency dependent upon the clock signal. Circuitry (118, 120, 138) is included for providing first and second pairs of quadrature phase shifted signals derived from the clock signal F.sub.clk and the low frequency signal F.sub.c and from the oscillator signal F.sub.o, respectively.