Patents by Inventor Scott D. Rodgers

Scott D. Rodgers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10592421
    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Carlos V. Rozas, Ilya Alexandrovich, Ittai Anati, Alex Berenzon, Michael A. Goldsmith, Barry E. Huntley, Anton Ivanov, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Rinat Rappoport, Scott D. Rodgers, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith, William C. Wood
  • Patent number: 10503662
    Abstract: Embodiments of systems, apparatuses, and methods for temporarily allowing access to a lower privilege level from a higher privilege level.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Martin G. Dixon, Gilbert Neiger, Robert S. Chappell, Scott D. Rodgers, Barry E. Huntley
  • Patent number: 10452403
    Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Hong Wang, John P. Shen, Edward T. Grochowski, Richard A. Hankins, Gautham N. Chinya, Bryant E. Bigbee, Shivnandan D. Kaushik, Xiang Chris Zou, Per Hammarlund, Scott Dion Rodgers, Xinmin Tian, Anil Aggawal, Prashant Sethi, Baiju V. Patel, James P Held
  • Publication number: 20190121751
    Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.
    Type: Application
    Filed: September 18, 2018
    Publication date: April 25, 2019
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard Uhlig, Lawrence Smith, III, Scott D. Rodgers
  • Publication number: 20190089709
    Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.
    Type: Application
    Filed: November 19, 2018
    Publication date: March 21, 2019
    Inventors: Barry E. HUNTLEY, Gilbert NEIGER, H. Peter ANVIN, Asit K. MALLICK, Adriaan VAN DE VEN, Scott D. RODGERS
  • Patent number: 10135825
    Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: November 20, 2018
    Assignee: Intel Corporation
    Inventors: Barry E. Huntley, Gilbert Neiger, H. Peter Anvin, Asit K. Mallick, Adriaan Van De Ven, Scott D. Rodgers
  • Patent number: 10114767
    Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard UhligQ, Lawrence Smith, III, Scott D. Rodgers
  • Patent number: 9537738
    Abstract: In an embodiment, a processor includes at least one core to execute instructions and a system management monitor to receive a platform query request from an external system, obtain status information regarding a configuration of one or more privileged resources of the processor, and report the status information to the external system. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: January 3, 2017
    Assignee: Intel Corporation
    Inventors: Brian Delgado, Brian S. Payne, Barry E. Huntley, Scott D. Rodgers
  • Publication number: 20160371191
    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 22, 2016
    Inventors: CARLOS V. ROZAS, ILYA ALEXANDROVICH, ITTAI ANATI, ALEX BERENZON, MICHAEL A. GOLDSMITH, BARRY E. HUNTLEY, ANTON IVANOV, SIMON P. JOHNSON, REBEKAH M. LESLIE-HURD, FRANCIS X. MCKEEN, GILBERT NEIGER, RINAT RAPPOPORT, SCOTT D. RODGERS, UDAY R. SAVAGAONKAR, VINCENT R. SCARLATA, VEDVYAS SHANBHOGUE, WESLEY H. SMITH, WILLIAM C. WOOD
  • Patent number: 9405937
    Abstract: A processor and method are described for managing different privilege levels associated with different types of program code, including binary translation program code. For example, one embodiment of a method comprises entering into one of a plurality of privilege modes responsive to detecting the execution of a corresponding one of a plurality of different types of program code including native executable program code, translated executable program code, and binary translation program code. In one embodiment, the binary translation program code includes sub-components each of which are associated with a different privilege level for improved security.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: August 2, 2016
    Assignee: INTEL CORPORATION
    Inventors: Lior Malka, Koichi Yamada, Palanivelrajan Shanmugavelayutham, Barry E. Huntley, Scott D. Rodgers, James D. Beaney, Jr.
  • Patent number: 9405551
    Abstract: In an embodiment, a processor includes a binary translation (BT) container having code to generate a binary translation of a first code segment and to store the binary translation in a translation cache, a host entity logic to manage the BT container and to identify the first code segment, and protection logic to isolate the BT container from a software stack. In this way, the BT container is configured to be transparent to the software stack. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: August 2, 2016
    Assignee: Intel Corporation
    Inventors: Koichi Yamada, Palanivel Rajan Shanmugavelayutham, Scott D. Rodgers, Barry E. Huntley, James D. Beaney, Jr., Boaz Tamir
  • Patent number: 9405570
    Abstract: Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claimed.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: August 2, 2016
    Assignee: Intel Corporation
    Inventors: Ravi L. Sahita, David M. Durham, Gilbert Neiger, Andrew V. Anderson, Scott D. Rodgers
  • Publication number: 20160191525
    Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Applicant: Intel Corporation
    Inventors: Barry E. Huntley, Gilbert NEIGER, H P. ANVIN, Asit K. MALLICK, Arjan VAN DE VEN, Scott D. RODGERS
  • Publication number: 20150381442
    Abstract: In an embodiment, a processor includes at least one core to execute instructions and a system management monitor to receive a platform query request from an external system, obtain status information regarding a configuration of one or more privileged resources of the processor, and report the status information to the external system. Other embodiments are described and claimed.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Inventors: Brian Delgado, Brian S. Payne, Barry E. Huntley, Scott D. Rodgers
  • Patent number: 9164920
    Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: October 20, 2015
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard UhligQ, Lawrence Smith, III, Scott D. Rodgers
  • Publication number: 20150178078
    Abstract: Instructions and logic provide base register swap status verification functionality. Embodiments include a processor having a first model specific register (MSR) to store a first base address corresponding to a segment for a first execution context and a second MSR to store a second base address corresponding to a segment for a second context. A third register stores a base register swap status field corresponding to the segment of the first and second contexts. A decode unit decodes a swap instruction and execution logic executes an exchange of the first MSR value and the second MSR value responsive to the swap instruction. The execution logic determines if said exchange of the first MSR value and the second MSR value completed successfully, and changes a value of the base register swap status field responsive to a determination that said exchange completed successfully.
    Type: Application
    Filed: December 21, 2013
    Publication date: June 25, 2015
    Inventors: H. Peter Anvin, Scott D. Rodgers
  • Patent number: 9032232
    Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 12, 2015
    Assignee: Intel Corporation
    Inventors: Martin G. Dixon, Scott D. Rodgers, Taraneh Bahrami, Stephen H. Gunther, Prashant Sethi, Per Hammarlund
  • Publication number: 20150100717
    Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.
    Type: Application
    Filed: December 12, 2014
    Publication date: April 9, 2015
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard UhligQ, Lawrence Smith, III, Scott D. Rodgers
  • Patent number: 8990597
    Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: March 24, 2015
    Assignee: Intel Corporation
    Inventors: Martin G. Dixon, Scott D. Rodgers, Taraneh Bahrami, Stephen H. Gunther, Prashant Sethi, Per Hammarlund
  • Publication number: 20150007304
    Abstract: A processor and method are described for managing different privilege levels associated with different types of program code, including binary translation program code. For example, one embodiment of a method comprises entering into one of a plurality of privilege modes responsive to detecting the execution of a corresponding one of a plurality of different types of program code including native executable program code, translated executable program code, and binary translation program code. In one embodiment, the binary translation program code includes sub-components each of which are associated with a different privilege level for improved security.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Lior Malka, Koichi Yamada, Palanivelrajan Shanmugavelayutham, Barry E. Huntley, Scott D. Rodgers, James D. Beaney, JR.