Abstract: A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. Further, a differential pre-charge operation can also be used in another embodiment. The ROM embedded DRAM allows for simplifier fabrication and programming of the ROM cells, while providing accurate dual state functionality.

Abstract: A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. Further, a differential pre-charge operation can also be used in another embodiment. The ROM embedded DRAM allows for simplifier fabrication and programming of the ROM cells, while providing accurate dual state functionality.

Abstract: Error correction through the use of on memory encoded error correction circuitry or parity checking circuitry allow for error correction in a read only memory (ROM) embedded dynamic random access memory (DRAM).

Abstract: A DRAM improves cell read margins using bias, or reference, circuitry. The reference circuitry is coupled to a complimentary digit line to improve a differential voltage with an active digit line. One embodiment, improves one's margin by decreasing the complimentary digit line voltage. The reference circuitry can be an unprogrammed DRAM cell, a non-volatile ROM memory cell or a conductor coupled to a reference voltage.

Abstract: A half-density ROM embedded DRAM uses hard programmed non-volatile cells and unprogrammed dynamic cells. By hard programming either a first or second memory cell in a pair of cell, different data states are stored. Two word lines are used to access the memory cell pair. Because one of the cells is hard programmed, sense amplifier circuitry identifies the appropriate data state. The ROM cell can be programmed in numerous different manners. For example, ROM cells can be hard programmed by eliminating cell dielectric to short cell plates to a program voltage, or an electrical plug can be fabricated between the cell plates and shorted to a program voltage. In other embodiments, the ROM cell can be programmed using an anti-fuse programming technique, or by providing a high leakage path (not full short) such as through an active area to the substrate.

Abstract: A ROM embedded DRAM allows hard programming of ROM cells by shorting DRAM capacitor plates during fabrication. In one embodiment, the intermediate dielectric layer is removed and the plates are shorted with a conductor. In another embodiment, an upper conductor and dielectric are removed and a conductor is fabricated in contact with the DRAM storage plate. The memory allows ROM cells to be hard programmed to different data states, such as Vcc and Vss.

Abstract: A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. Further, a differential pre-charge operation can also be used in another embodiment. The ROM embedded DRAM allows for simplifier fabrication and programming of the ROM cells, while providing accurate dual state functionality.

Abstract: A voltage regulator is disclosed which is coupled with a programmable trimming circuit by a trim test circuit. When disabled, the trim test circuit passes the logic states of the signals produced by the trimming circuit to the voltage regulator. When enabled, the trim test circuit applies signals to the voltage regulator which correspond with asserted logic states of signals producible by the trimming circuit. Thus, the effect of the trimming circuit on the voltage regulator is testable without actual programming of the trimming circuit.

Abstract: A voltage regulator is disclosed which is coupled with a programmable trimming circuit by a trim test circuit. When disabled, the trim test circuit passes the logic states of the signals produced by the trimming circuit to the voltage regulator. When enabled, the trim test circuit applies signals to the voltage regulator which correspond with asserted logic states of signals producible by the trimming circuit. Thus, the effect of the trimming circuit on the voltage regulator is testable without actual programming of the trimming circuit.