Abstract: Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.

Abstract: Methods, systems, and devices for refresh counters in a memory system are described. In some examples, a memory device may include two or more counters configured to increment a respective count based on refresh operations performed on a memory array. A comparison may be made between two or more of the respective counts, which may include determining a difference between the respective counts or a difference in rate of incrementing. A memory device may transmit an indication to a host device based on determining a difference between counters, and the memory device, the host device, or both, may perform various operations or enter various operational modes based on the determined difference.

Abstract: Implementations described herein relate to performing a memory built-in self-test and indicating a status of the memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is enabled. The memory device may set a DMI bit of the memory device to a first value and perform the memory built-in self-test based on identifying that the memory built-in self-test is enabled. The memory device may set the DMI bit of the memory device to a second value based on a completion of the memory built-in self-test.

Abstract: Methods, systems, and devices for address verification at a memory device are described. The memory device may receive a read command for a read address. Based on the read command, the memory device may read data from the read address and a first set of error detection bits that is based on a write address associated with the data. The memory device may generate, based on the first set of error detection bits and a second set of error detection bits that is based on the read address, an address match signal that indicates whether the read address matches the write address. And the memory device may provide the data and an indication of the address match signal to a host device.

Abstract: Methods, systems, and devices for redundancy-based error detection in a memory device are described. A memory device may read multiple copies of a codeword from memory and generate for each codeword copy an error detection bit that indicates whether the memory device detected an error in that codeword. Additionally, the memory device may compare the codeword copies and generate one or more match bits that indicate whether corresponding portions of the codewords match. Using a combination of the error detection bits and the match bits, the memory device may determine the error status of each codeword.

Abstract: Methods, systems, and devices for error detection and classification are described. A memory device may read a codeword from a memory and generate a first set of syndrome bits for the codeword. The memory device may use the first set of syndrome bits to generate a first error detection bit. The memory device may generate a second set of syndrome bits for the codeword and use the second set of syndrome bits to generate a second error detection bit. The memory device may provide the first error detection bit and the second error detection bit to a host device.

Abstract: Methods, systems, and devices for error detection and classification at a host device are described. A host device may communicate a read command for a codeword stored at a memory device. In response to communicating the read command, the host device may receive the codeword and an error indication bit that indicates whether the memory device detected an error in the codeword. The host device may use the codeword to generate a set of syndrome bits. The host device may determine an error status of the codeword based on the error indication bit for the codeword and the set of syndrome bits for the codeword.

Abstract: Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.

Abstract: Methods, systems, and devices for error status determination at a memory device are described. A memory device may generate, based on syndrome bits for a codeword read from a memory, an error detection signal for the codeword that indicates whether an error has been detected in the codeword. The memory device may generate, based on the syndrome bits, an error correction signal for the codeword that indicates whether an error has been corrected in the codeword. And the memory device may provide an indication of the error detection signal and an indication of the error correction signal to a host device.

Abstract: Methods, systems, and devices for coordinated error correction are described. A memory device may indicate, for example to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. After performing the comparison, an indication of or based on whether the compared error correction codes match may be provided to the external device. The external device may use the indication to detect errors in the received version of the data, or to manage data storage in the memory device, or both, among other operations.

Abstract: Methods, systems, and devices for life expectancy monitoring for memory devices are described. A memory device may monitor a parameter of a component of the memory device or the memory device overall, and may determine whether the parameter satisfies a threshold. The parameter may represent or be associated with a lifetime of the component, a level of wear of the component, or an operating parameter violation of the component, or any combination thereof. The memory device may communicate, to a host device, an indication of the parameter satisfying the threshold, and the host device may use the information in the indication to adjust one or more parameters associated with operating the memory device, among other example operations.

Abstract: Methods, systems, and devices for redundancy-based error detection in a memory device are described. A memory device may read multiple copies of a codeword from memory and generate for each codeword copy an error detection bit that indicates whether the memory device detected an error in that codeword. Additionally, the memory device may compare the codeword copies and generate one or more match bits that indicate whether corresponding portions of the codewords match. Using a combination of the error detection bits and the match bits, the memory device may determine the error status of each codeword.

Abstract: Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.

Abstract: Methods, systems, and devices for techniques for indicating a write link error are described. The method may include a memory device receiving, from a host device, a write command, data, and a first set of error control bits for the data. The memory device may determine that the data includes an uncorrectable error using the first set of error control bits and generate a second set of error control bits for the data based on determining that the data includes the uncorrectable error. Further, the method may include the memory device storing the data and the second set of error control bits in a memory device and transmitting, to the host device, the data and an indication that the data received from the host device included the uncorrectable error based on the second set of error control bits.

Abstract: Methods, systems, and devices for coordinated error protection are described. A set of data and an indication of whether a first management procedure performed by a memory device on the set of data detected one or more errors in the set of data may be received at a host device. At the host device, a second error management procedure may be performed on the set of data received from the memory device. Based on the received indication and the second error management procedure, multiple bits indicating whether one or more errors associated with the set of data were detected at the memory device, the host device, or both may be generated. The set of data may be validated or discarded based on the multiple bits.

Abstract: Implementations described herein relate to performing a memory built-in self-test and indicating a status of the memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is enabled. The memory device may set a DMI bit of the memory device to a first value and perform the memory built-in self-test based on identifying that the memory built-in self-test is enabled. The memory device may set the DMI bit of the memory device to a second value based on a completion of the memory built-in self-test.

Abstract: Methods, systems, and devices for reset verification in a memory system are described. In some examples, a memory device may perform a reset operation and set a mode register to a first value based on performing the reset operation. The first value may be associated with a successful execution of the reset command. The memory device may transmit an indication to a host device based on determining the first value. The host device may determine from the received indication or from the first value stored in the mode register that the first value is associated with the successful execution of the reset command. Thus, the memory device, or the host device, or both may be configured to verify whether the reset operation is successful.

Abstract: Methods, systems, and devices for performing memory command verification are described. A system may include a memory device and a memory controller, which may be external (e.g., a host device). The memory device may receive, from the memory controller, a command indicating a type of operation and an address. The memory device may decode the command and execute an operation (e.g., the operation corresponding to the decoded command) at an execution location on the memory device. The system (e.g., the memory device or the memory controller) may determine whether the executed operation and execution location match the type of operation and address indicated in the command, and the system may thereby determine an error associated with the decoding, the execution, or both of the command.

Abstract: Implementations described herein relate to single-bit error indication for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may perform the memory built-in self-test for one or more memory sections of the memory device based on reading the one or more bits that are stored in the mode register of the memory device. The memory device may identify a number of single-bit errors associated with the one or more memory sections of the memory device based on performing the memory built-in self-test. The memory device may transmit an indication of the number of single-bit errors based on repairing one or more of the single-bit errors associated with the one or more memory sections of the memory device.

Abstract: Implementations described herein relate to resource allocation for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify one or more memory resources of the memory device, based on reading the one or more bits, that are to be used for performing the memory built-in self-test. The one or more memory resources of the memory device may be addressable memory resources configured for performing standard memory operations of the memory device. The memory device may perform the memory built-in self-test for the memory device using the one or more memory resources of the memory device.