Abstract: Methods, systems, and devices for metadata for indication of access authorization in a memory system are described. Some memory systems may not permit access to data stored within the memory system by a host system until the host system and corresponding access request are verified. If a host system attempts to access the memory system and is not verified, the memory system described herein may send invalid data or poisoned data back to the host system in addition to metadata that indicates that the host system was not verified to access the memory system. The metadata may include multiple bits associated with multiple candidate values. At least one value of the multiple candidate values may be reserved for indicating that an access request was denied due to a failed verification of the host system. The host system may use the metadata to improve subsequent access requests.

Abstract: Methods, systems, and devices for increased memory reliability via redundancy are described. The memory system may receive a write command associated with data to be written to the memory system and write the data to a first portion of the memory system and a copy of the data to a second portion of the memory system based on the write command. After writing the data and the copy of the data, the memory system may receive a read command for the data and read the data from the first portion and the copy of the data from the second portion based on the read command. After reading the data and the copy of the data, the memory system may perform an error control operation on the data and the copy of the data and transmit the data or the copy of the data based on performing the error control operation.

Abstract: Methods, systems, and devices for component level error correction code (ECC) for data protection are described. An ECC component may be added to a memory system that may be configured to perform error correction for data stored within multiple memory dies in the memory system using parity bits from one or more of the memory dies. For example, on-die ECC may disabled at one or more of the memory dies and one or more parity bits previously used for on-die error correction by the one or more memory dies may be transferred from the memory dies to the ECC component for use in the component-level error correction. That is, instead of correcting data at each memory die, the data and one or more parity bits may be transferred to the ECC component and combined for error correction within the ECC component.

Abstract: Methods, systems, and devices for dedicated channels for data transmission are described. A receiving device may receive, from a transmitting device, first data via a first channel and second data via a second channel (e.g., a redundant channel). The receiving device may perform one or more error control operations on the first data and the second data, and may select a channel for additional communications if one or more errors are detected in the data. The receiving device may also select a channel if the channel is indicated by a stored parameter. In some examples, the receiving device may transmit feedback in third data via the first channel, via the redundant channel, or both, which may be used by a transmitting device to detect or correct one or more errors, or for training operations.

Abstract: Methods, systems, and devices for dynamic error correction schemes for memory systems are described. A memory system may include an error control component and one or more memory devices coupled with the error control component. The memory system may be configured to detect one or more trigger conditions for adjusting an error control operation of a memory system. The memory system may select an error control scheme from a plurality of error control schemes that are implemented by the error control component based on detecting the one or more trigger conditions. The error control component of the memory system may use the selected error control scheme to perform one or more error control operations to protect data stored at the one or more memory devices.

Abstract: Methods, systems, and devices for error log indication via error control information are described. For instance, a memory device may transmit, to a host device, a first signal including a set of error control bits indicating that an error log of the memory device includes information for use by the host device. The memory device may receive, from the host device in response to the first signal, a second signal including a request to retrieve the information of the error log. The memory device may transmit, to the host device in response to the second signal, a third signal including the information of the error log.

Abstract: Methods, systems, and devices for address verification at a memory device are described. The memory device may receive a read command for a read address. Based on the read command, the memory device may read data from the read address and a first set of error detection bits that is based on a write address associated with the data. The memory device may generate, based on the first set of error detection bits and a second set of error detection bits that is based on the read address, an address match signal that indicates whether the read address matches the write address. And the memory device may provide the data and an indication of the address match signal to a host device.

Abstract: Methods, systems, and devices for error detection and classification are described. A memory device may read a codeword from a memory and generate a first set of syndrome bits for the codeword. The memory device may use the first set of syndrome bits to generate a first error detection bit. The memory device may generate a second set of syndrome bits for the codeword and use the second set of syndrome bits to generate a second error detection bit. The memory device may provide the first error detection bit and the second error detection bit to a host device.

Abstract: Implementations described herein relate to enabling or disabling on-die error-correcting code for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, whether the memory built-in self-test is to be performed with on-die error-correcting code (ECC) disabled or with on-die ECC enabled. The memory device may perform the memory built-in self-test, and selectively test for one or more single-bit errors, based on identifying whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled.

Abstract: Implementations described herein relate to test mode monitoring and feedback. In some implementations, a memory apparatus may detect, by a test mode monitor component of the memory apparatus, that the memory apparatus has entered a test mode based on one or more test mode signals. The memory apparatus may provide, to a host system, a message indicating that the memory apparatus has entered the test mode.

Abstract: Implementations described herein relate to single-bit error indication for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may perform the memory built-in self-test for one or more memory sections of the memory device based on reading the one or more bits that are stored in the mode register of the memory device. The memory device may identify a number of single-bit errors associated with the one or more memory sections of the memory device based on performing the memory built-in self-test. The memory device may transmit an indication of the number of single-bit errors based on repairing one or more of the single-bit errors associated with the one or more memory sections of the memory device.

Abstract: Methods, systems, and devices for differential strobe fault indication are described. A memory device may be configured to indicate a fault using a read strobe signal. The read strobe signal may be a read data strobe (RDQS) signal, such as a true RDQS (RDQS_t) signal or a complement RDQS (RDQS_c) signal. In some examples, the memory device may indicate the fault based on a characteristic of the read strobe signal, such as a pattern of the read strobe signal, a voltage level of the read strobe signal, a difference between a first read strobe signal and a second read strobe signal, or any combination thereof. In some examples, a host device may identify a fault type (e.g., recoverable or unrecoverable) based on a fault signature associated with a given characteristic of the read strobe signal. The host device may perform recovery operations based on the fault type identified.

Abstract: Methods, systems, and devices for coordinated error protection are described. A set of data and an indication of whether a first management procedure performed by a memory device on the set of data detected one or more errors in the set of data may be received at a host device. At the host device, a second error management procedure may be performed on the set of data received from the memory device. Based on the received indication and the second error management procedure, multiple bits indicating whether one or more errors associated with the set of data were detected at the memory device, the host device, or both may be generated. The set of data may be validated or discarded based on the multiple bits.

Abstract: Methods, systems, and devices for coordinated error correction are described. A memory device may indicate, for example to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. After performing the comparison, an indication of or based on whether the compared error correction codes match may be provided to the external device. The external device may use the indication to detect errors in the received version of the data, or to manage data storage in the memory device, or both, among other operations.

Abstract: Methods, systems, and devices for selective modes for error control are described. A memory system may implement an error control engine supporting error correction operations and error detection operations. The error control engine may switch between an error correction mode and an error detection mode. The error control engine may receive data and error control information, generate additional error control information, and compare the received and generated error control information to detect one or more errors in the data. In some examples, the error control engine may be configured to operate in the error correction mode, and the error control engine may correct single-bit errors in the data. In other examples, the error control engine may be configured to operate in the error detection mode, and the error control engine may detect errors in the data and transmit an indication of the errors.

Abstract: Methods, systems, and devices for address verification at a memory device are described. The memory device may receive a read command for a read address. Based on the read command, the memory device may read data from the read address and a first set of error detection bits that is based on a write address associated with the data. The memory device may generate, based on the first set of error detection bits and a second set of error detection bits that is based on the read address, an address match signal that indicates whether the read address matches the write address. And the memory device may provide the data and an indication of the address match signal to a host device.

Abstract: Methods, systems, and devices for evaluation of memory device health monitoring logic are described. For example, a memory device may include health monitoring logic operable to activate certain internal health monitors of a set of multiple monitors and to communicate an output associated with the activated monitors. In a first mode of operation, the health monitoring logic may provide a single output that is generated from multiple outputs of the set of monitors. In a second mode of operation, the health monitoring logic may cycle through certain monitors (e.g., in a test mode), and may generate an output corresponding to respective active monitors as it cycles through the set of monitors. The health monitoring logic may communicate an output specific to each monitor to a host device such that the host device may evaluate an output from each monitor of the set of monitors.

Abstract: Implementations described herein relate to single-bit error indication for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may perform the memory built-in self-test for one or more memory sections of the memory device based on reading the one or more bits that are stored in the mode register of the memory device. The memory device may identify a number of single-bit errors associated with the one or more memory sections of the memory device based on performing the memory built-in self-test. The memory device may transmit an indication of the number of single-bit errors based on repairing one or more of the single-bit errors associated with the one or more memory sections of the memory device.

Abstract: Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.

Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may fail to receive or decode (e.g., successfully receive or successfully decode) an access command transmitted to the memory device via a bus. The bus may enter or remain in an idle state which may cause indeterminate signals to develop on the idle bus. A host device may obtain the indeterminate signals from the idle bus and determine that the indeterminate signals include an error based on a signal that develops on a control line of the idle bus. The signal may be associated with a control signal that indicates errors in a data signal when the control signal has a first voltage, and the control line may be configured to have the first voltage when the bus is idle.