Abstract: Methods, systems, and devices for error detection and classification are described. A memory device may read a codeword from a memory and generate a first set of syndrome bits for the codeword. The memory device may use the first set of syndrome bits to generate a first error detection bit. The memory device may generate a second set of syndrome bits for the codeword and use the second set of syndrome bits to generate a second error detection bit. The memory device may provide the first error detection bit and the second error detection bit to a host device.

Abstract: Implementations described herein relate to enabling or disabling on-die error-correcting code for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, whether the memory built-in self-test is to be performed with on-die error-correcting code (ECC) disabled or with on-die ECC enabled. The memory device may perform the memory built-in self-test, and selectively test for one or more single-bit errors, based on identifying whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled.

Abstract: Implementations described herein relate to test mode monitoring and feedback. In some implementations, a memory apparatus may detect, by a test mode monitor component of the memory apparatus, that the memory apparatus has entered a test mode based on one or more test mode signals. The memory apparatus may provide, to a host system, a message indicating that the memory apparatus has entered the test mode.

Abstract: Implementations described herein relate to single-bit error indication for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may perform the memory built-in self-test for one or more memory sections of the memory device based on reading the one or more bits that are stored in the mode register of the memory device. The memory device may identify a number of single-bit errors associated with the one or more memory sections of the memory device based on performing the memory built-in self-test. The memory device may transmit an indication of the number of single-bit errors based on repairing one or more of the single-bit errors associated with the one or more memory sections of the memory device.

Abstract: Methods, systems, and devices for differential strobe fault indication are described. A memory device may be configured to indicate a fault using a read strobe signal. The read strobe signal may be a read data strobe (RDQS) signal, such as a true RDQS (RDQS_t) signal or a complement RDQS (RDQS_c) signal. In some examples, the memory device may indicate the fault based on a characteristic of the read strobe signal, such as a pattern of the read strobe signal, a voltage level of the read strobe signal, a difference between a first read strobe signal and a second read strobe signal, or any combination thereof. In some examples, a host device may identify a fault type (e.g., recoverable or unrecoverable) based on a fault signature associated with a given characteristic of the read strobe signal. The host device may perform recovery operations based on the fault type identified.

Abstract: Methods, systems, and devices for coordinated error protection are described. A set of data and an indication of whether a first management procedure performed by a memory device on the set of data detected one or more errors in the set of data may be received at a host device. At the host device, a second error management procedure may be performed on the set of data received from the memory device. Based on the received indication and the second error management procedure, multiple bits indicating whether one or more errors associated with the set of data were detected at the memory device, the host device, or both may be generated. The set of data may be validated or discarded based on the multiple bits.

Abstract: Methods, systems, and devices for coordinated error correction are described. A memory device may indicate, for example to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. After performing the comparison, an indication of or based on whether the compared error correction codes match may be provided to the external device. The external device may use the indication to detect errors in the received version of the data, or to manage data storage in the memory device, or both, among other operations.

Abstract: Methods, systems, and devices for selective modes for error control are described. A memory system may implement an error control engine supporting error correction operations and error detection operations. The error control engine may switch between an error correction mode and an error detection mode. The error control engine may receive data and error control information, generate additional error control information, and compare the received and generated error control information to detect one or more errors in the data. In some examples, the error control engine may be configured to operate in the error correction mode, and the error control engine may correct single-bit errors in the data. In other examples, the error control engine may be configured to operate in the error detection mode, and the error control engine may detect errors in the data and transmit an indication of the errors.

Abstract: Methods, systems, and devices for address verification at a memory device are described. The memory device may receive a read command for a read address. Based on the read command, the memory device may read data from the read address and a first set of error detection bits that is based on a write address associated with the data. The memory device may generate, based on the first set of error detection bits and a second set of error detection bits that is based on the read address, an address match signal that indicates whether the read address matches the write address. And the memory device may provide the data and an indication of the address match signal to a host device.

Abstract: Methods, systems, and devices for evaluation of memory device health monitoring logic are described. For example, a memory device may include health monitoring logic operable to activate certain internal health monitors of a set of multiple monitors and to communicate an output associated with the activated monitors. In a first mode of operation, the health monitoring logic may provide a single output that is generated from multiple outputs of the set of monitors. In a second mode of operation, the health monitoring logic may cycle through certain monitors (e.g., in a test mode), and may generate an output corresponding to respective active monitors as it cycles through the set of monitors. The health monitoring logic may communicate an output specific to each monitor to a host device such that the host device may evaluate an output from each monitor of the set of monitors.

Abstract: Implementations described herein relate to single-bit error indication for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may perform the memory built-in self-test for one or more memory sections of the memory device based on reading the one or more bits that are stored in the mode register of the memory device. The memory device may identify a number of single-bit errors associated with the one or more memory sections of the memory device based on performing the memory built-in self-test. The memory device may transmit an indication of the number of single-bit errors based on repairing one or more of the single-bit errors associated with the one or more memory sections of the memory device.

Abstract: Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.

Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may fail to receive or decode (e.g., successfully receive or successfully decode) an access command transmitted to the memory device via a bus. The bus may enter or remain in an idle state which may cause indeterminate signals to develop on the idle bus. A host device may obtain the indeterminate signals from the idle bus and determine that the indeterminate signals include an error based on a signal that develops on a control line of the idle bus. The signal may be associated with a control signal that indicates errors in a data signal when the control signal has a first voltage, and the control line may be configured to have the first voltage when the bus is idle.

Abstract: Methods, systems, and devices for uncorrectable error detection in memory systems are described. A memory system may perform a syndrome check to compare a first syndrome with a second syndrome, the first syndrome being generated as part of a first error control operation performed on data and the second syndrome being generated as part of a second error control operation performed on the data. Based on performing the syndrome check, the memory system may generate a first flag that indicates whether the first syndrome is equivalent to the second syndrome. The memory system may generate a second flag that indicates whether the second error control operation resulted in one or more bits of the data being modified. Based on the first and second flags, the memory system may generate a third flag that indicates whether an uncorrectable error is detected in the data during the second error control operation.

Abstract: In some implementations, a memory device may receive a command. The memory device may receive, subsequent to the command, a parity check command, where the parity check command includes a set of parity bits relating to the command. The memory device may perform a parity check for the command using the set of parity bits.

Abstract: Methods, systems, and devices for on-die error detection and correction for meta data are described. A memory system may receive a write command associated with a first set of bits that includes data bits and meta data bits associated with the data bits and generate a second set of bits based on inputting the first set of bits into an error correction encoder. The second set of bits may include the data bits, the meta data bits, and parity bits. Upon generating the second set of bits, the memory system may store the meta data bits in at least a portion of a first memory space of the memory array of the memory system. The memory array may include the first memory space allocated for meta data and a second memory space allocated for data.

Abstract: In some implementations, a memory device may receive a mode register command that configures a parameter in a mode register of the memory device. The memory device may receive a set of command bits that indicates a command, where configuration of the parameter in the mode register frees a switchable parameter bit, of the set of command bits, that otherwise is used to configure the parameter, and where the switchable parameter bit is used as a parity bit relating to remaining bits of the set of command bits. The memory device may perform a parity check using the switchable parameter bit that is used as the parity bit.

Abstract: Methods, systems, and devices for alert signaling in memory systems are described. A memory system may maintain a first mode register that includes multiple operands, where each operand corresponds to a respective fault that may occur in the memory system. The memory system may also maintain a second mode register that is associated with the first mode register, where each operand of the second mode register corresponds to one or more operands of the first mode register. A value of each operand of the second mode register may indicate whether the memory system is to drive the alert output in response to detection of the corresponding fault. As such, if a first operand of the first mode register is set, indicating a fault has occurred, and a first operand of the second mode register indicates for the alert output to be driven, the memory system may drive the alert output.

Abstract: Methods, systems, and devices for coordinated error correction are described. A memory device indicates, for example to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. Based on the comparison, an indication of or based on whether the compared error correction codes match is provided to the external device. The external device uses the indication to detect errors in the received version of the data, or to manage data storage in the memory device, or both.

Abstract: Methods, systems, and devices for temperature monitoring for memory devices are described for monitoring one or more temperature ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more temperature ranges. The memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. The indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. The host device may use information included in the indication to perform an operation associated with the memory device.