Abstract: Methods, systems, and devices for information logging via a sideband within a memory system are described. One or more memory devices within a memory system may communicate with a baseboard management controller (BMC) via a sideband. Such communication may support relatively granular logging of information associated with the memory system. For example, the memory system may monitor one or more parameters associated with the memory system and may transmit, via the sideband, log information that logs the metrics over time. The memory system may perform the monitoring and logging concurrently with communications exchanged between the memory system and a host system via an in-band link and other corresponding access operations. The memory system may perform associated operations based on the log information during one or more idle times, to reduce interference with access operations.

Abstract: Methods, systems, and devices for host error control matrix are described. A host device may implement a parity check matrix for generating error control information with a relatively low likelihood that a multi-bit error in a codeword associated with the error control information is mistaken for a single-bit error. The host device may implement a parity check matrix patterned such that when the error control information is generated, there is a relatively low likelihood that an error code resulting from a comparison of the error control information will yield an indication of a single-bit error when a multi-bit error occurs. For example, the host device may compare first error control information generated for a codeword and transmitted to a memory device with second error control information generated after receiving the codeword from the memory device, and generate an error code using the results of the comparison.

Abstract: Methods, systems, and devices for command address error control are described. The memory system may receive command address (CA) information and error control information associated with the CA information. The memory system may perform an error control operation on the CA information using the error control information by determining whether the CA information includes one or more errors using the error control information and perform an operation associated with the CA information based on performing the error control operation.

Abstract: In some implementations, a memory apparatus may obtain, from a host system, a message comprising data to be stored to one or more memory arrays of a memory apparatus. The memory apparatus may perform, based at least in part on operating in an error detection mode, an error detection operation associated with the error detection mode on the data and an error correction operation associated with an error correction mode on the data. The memory apparatus may provide, as part of the error detection mode, a first one or more values associated with the error detection operation and a second one or more values associated with the error correction operation.

Abstract: Methods, systems, and devices for dynamic scrambling for wired communications between systems are described. A host system may transmit a first packet of data bits to a memory system. The host system may receive an indication that the memory system received the first packet with a threshold quantity of one or more errors. Based on receiving the indication, the host system may apply a scrambling pattern to a second packet of the data bits. The host system may then transmit the second data packet to the memory system based on applying the scrambling pattern to the second data packet.

Abstract: Implementations described herein relate to interrupting a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is to be interrupted while the memory built-in self-test is being performed using a test mode. The memory device may be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode but may not be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using a repair mode. The memory device may interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode.

Abstract: Methods, systems, and devices for memory device health monitoring logic are described. In accordance with examples as disclosed herein, a memory device may include health monitoring logic configured to monitor a degradation level of the memory device. Further, the health monitoring logic may include a self-check logic to monitor the degradation level of the health monitoring logic. Using the health monitoring logic, the memory device may evaluate and store a health state of the memory device, which may be used to flag a fault in the memory device, among other responsive operations. Additionally, using the self-check logic, the memory device may evaluate and store a health state of the health monitoring logic, which may be used to flag a fault of the previously evaluated health state of the memory device. Based on the self-check flag, a host device may halt or adjust the response operations associated with the memory device.

Abstract: In some implementations, a memory apparatus may obtain, from a host system, a first message including data and parity information associated with the data. The memory apparatus may perform an error control operation on the data using the parity information. The memory apparatus may store the data and the parity information to the memory apparatus.

Abstract: Methods, systems, and devices for determination of errors as link-driven or die-driven errors are described. Generation of redundancy information and parity information for data protection may be split across an interface between a memory system and a host system to improve error detection. The memory system may receive, from the host system via an interface, data and redundancy information associated with the data. The memory system may use the redundancy information to check for errors caused by transfer of the data via the interface. The memory system may request a retransmission or perform an error correction if an error is detected. After the errors in the data due to the interface transmission are corrected, the memory system may generate parity information associated with the data and write the data, the parity information, and the redundancy information to one or more memory devices of the memory system.

Abstract: Methods, systems, and devices for differential strobe fault indication are described. A memory device may be configured to indicate a fault using a read strobe signal. The read strobe signal may be a read data strobe (RDQS) signal, such as a true RDQS (RDQS_t) signal or a complement RDQS (RDQS_c) signal. In some examples, the memory device may indicate the fault based on a characteristic of the read strobe signal, such as a pattern of the read strobe signal, a voltage level of the read strobe signal, a difference between a first read strobe signal and a second read strobe signal, or any combination thereof. In some examples, a host device may identify a fault type (e.g., recoverable or unrecoverable) based on a fault signature associated with a given characteristic of the read strobe signal. The host device may perform recovery operations based on the fault type identified.

Abstract: Methods, systems, and devices for adjustment of error correction algorithms are described. A memory system may modify an error correction algorithm for different portions of memory within a memory array. For example, the memory system may receive commands to read data from a portion of the memory array, and the memory system may perform error correction of the data using parity information. The memory system may identify that the portion of memory includes a threshold quantity of errors exceeding the error correction capabilities associated with the parity information. In response, the memory system may determine to switch an error correction algorithm for the portion of the data from a first error correction algorithm to a second error correction algorithm. For example, the memory system may store an additional quantity of error correction bits to be used for error correction of the portion of memory during subsequent data accesses.

Abstract: Methods, systems, and devices for data buffer error correction functionality are described. A data buffer of a memory system may support system-level error correction capabilities. For example, the data buffer may be configured to perform error correction for data stored within multiple memory dies in the memory system using parity bits aggregated from one or more of the memory dies. In some examples, on-die error correction at one or more of the memory dies may be disabled. Extra parity bits previously used for on-die error correction may be transferred from the memory dies to the data buffer for use in the system-level error correction. The aggregation of the extra bits for error correction within the data buffer may improve a performance and reliability of the system-level error correction.

Abstract: In some implementations, a memory apparatus may obtain, from a host system, a first message comprising data and link parity information associated with the data. The memory apparatus may determine that the data includes one or more errors based on the link parity information. The memory apparatus may store a first value indicating that the data includes the one or more errors. The memory apparatus may provide, as part of a read request for the data, a second message comprising the data and a second value, the second value indicating that the data includes the one or more errors.

Abstract: In some implementations, a memory apparatus may obtain, from a host system, a command indicating that the memory apparatus is to provide data to the host system. The memory apparatus may identify a status of one or more fault mode registers based on the command. The memory apparatus may provide, to the host system, a message comprising the data and comprising the status of the one or more fault mode registers.

Abstract: Methods, systems, and devices for sub-channel switching using redundant pins are described. The described techniques may enable a host system to switch from communicating with a memory system via a first set of pins associated with a first sub-channel to communicating with the memory system via a second set of pins associated with a second sub-channel based on detecting a fault associated with the first set of pins. In some examples, the host system may communicate via both the first set of pins and the second set of pins. The memory system may perform a comparison between data received via the first set of pins and the second set of pins, and may indicate to the host system if a difference is detected. The host system may switch to communicating via one of the first set of pins or the second set of pins based on detecting the difference.

Abstract: Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.

Abstract: Methods, systems, and devices for metadata for indication of access authorization in a memory system are described. Some memory systems may not permit access to data stored within the memory system by a host system until the host system and corresponding access request are verified. If a host system attempts to access the memory system and is not verified, the memory system described herein may send invalid data or poisoned data back to the host system in addition to metadata that indicates that the host system was not verified to access the memory system. The metadata may include multiple bits associated with multiple candidate values. At least one value of the multiple candidate values may be reserved for indicating that an access request was denied due to a failed verification of the host system. The host system may use the metadata to improve subsequent access requests.

Abstract: Methods, systems, and devices for increased memory reliability via redundancy are described. The memory system may receive a write command associated with data to be written to the memory system and write the data to a first portion of the memory system and a copy of the data to a second portion of the memory system based on the write command. After writing the data and the copy of the data, the memory system may receive a read command for the data and read the data from the first portion and the copy of the data from the second portion based on the read command. After reading the data and the copy of the data, the memory system may perform an error control operation on the data and the copy of the data and transmit the data or the copy of the data based on performing the error control operation.

Abstract: Methods, systems, and devices for component level error correction code (ECC) for data protection are described. An ECC component may be added to a memory system that may be configured to perform error correction for data stored within multiple memory dies in the memory system using parity bits from one or more of the memory dies. For example, on-die ECC may disabled at one or more of the memory dies and one or more parity bits previously used for on-die error correction by the one or more memory dies may be transferred from the memory dies to the ECC component for use in the component-level error correction. That is, instead of correcting data at each memory die, the data and one or more parity bits may be transferred to the ECC component and combined for error correction within the ECC component.

Abstract: Methods, systems, and devices for dedicated channels for data transmission are described. A receiving device may receive, from a transmitting device, first data via a first channel and second data via a second channel (e.g., a redundant channel). The receiving device may perform one or more error control operations on the first data and the second data, and may select a channel for additional communications if one or more errors are detected in the data. The receiving device may also select a channel if the channel is indicated by a stored parameter. In some examples, the receiving device may transmit feedback in third data via the first channel, via the redundant channel, or both, which may be used by a transmitting device to detect or correct one or more errors, or for training operations.