Abstract: Implementations described herein relate to indicating a status of the memory built-in self-test for multiple memory device ranks. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify a first data mask inversion (DMI) bit of the memory device that is associated with a first rank of the memory device and a second DMI bit of the memory device that is associated with a second rank of the memory device. The memory device may set the first DMI bit to a first value based on determining to perform the memory built-in self-test for the first rank of the memory device. The memory device may perform the memory built-in self-test for the first rank of the memory device based on setting the first DMI bit to the first value.

Abstract: Methods, systems, and devices for memory device health monitoring logic are described. In accordance with examples as disclosed herein, a memory device may include health monitoring logic configured to monitor a degradation level of the memory device. Further, the health monitoring logic may include a self-check logic to monitor the degradation level of the health monitoring logic. Using the health monitoring logic, the memory device may evaluate and store a health state of the memory device, which may be used to flag a fault in the memory device, among other responsive operations. Additionally, using the self-check logic, the memory device may evaluate and store a health state of the health monitoring logic, which may be used to flag a fault of the previously evaluated health state of the memory device. Based on the self-check flag, a host device may halt or adjust the response operations associated with the memory device.

Abstract: Implementations described herein relate to interrupting a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is to be interrupted while the memory built-in self-test is being performed using a test mode. The memory device may be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode but may not be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using a repair mode. The memory device may interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode.

Abstract: Methods, systems, and devices for evaluation of memory device health monitoring logic are described. For example, a memory device may include health monitoring logic operable to activate certain internal health monitors of a set of multiple monitors and to communicate an output associated with the activated monitors. In a first mode of operation, the health monitoring logic may provide a single output that is generated from multiple outputs of the set of monitors. In a second mode of operation, the health monitoring logic may cycle through certain monitors (e.g., in a test mode), and may generate an output corresponding to respective active monitors as it cycles through the set of monitors. The health monitoring logic may communicate an output specific to each monitor to a host device such that the host device may evaluate an output from each monitor of the set of monitors.

Abstract: Methods, systems, and devices for memory die fault detection using a calibration pin are described. A memory device may perform a calibration procedure on a first resistor of each of a set of memory dies of a memory module using a pin coupled with the memory module. The memory device may couple the pin to a second resistor of a memory die of the set of memory dies based on the memory die identifying a fault condition for the memory die executing one or more of multiple commands from the host device. The memory device may receive, from the host device, a command to read a register of one or more memory dies of the set of memory dies and may output, to the host device, an indication of the memory die that identified the fault condition based on coupling the pin to the second resistor.

Abstract: Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.

Abstract: Methods, systems, and devices for syndrome check functionality to differentiate between error types are described. A host system, a memory system, or some combination of both may include syndrome check circuitry to provide enhanced error diagnostic capabilities for data communicated between the host system and the memory system. The syndrome check circuitry may receive a first signal from the memory system indicating whether the memory system detected and attempted to correct an error in the data and may receive a second signal from the host system indicating whether the host system detected an error in the received data. The syndrome check circuitry may compare the first signal and the second signal using a set of logic gates to differentiate between different combinations of errors detected at one or both of the memory system or the host system.

Abstract: Methods, systems, and devices for error log indication via error control information are described. For instance, a memory device may transmit, to a host device, a first signal including a set of error control bits indicating that an error log of the memory device includes information for use by the host device. The memory device may receive, from the host device in response to the first signal, a second signal including a request to retrieve the information of the error log. The memory device may transmit, to the host device in response to the second signal, a third signal including the information of the error log.

Abstract: Methods, systems, and devices for differential strobe fault indication are described. A memory device may be configured to indicate a fault using a read strobe signal. The read strobe signal may be a read data strobe (RDQS) signal, such as a true RDQS (RDQS_t) signal or a complement RDQS (RDQS_c) signal. In some examples, the memory device may indicate the fault based on a characteristic of the read strobe signal, such as a pattern of the read strobe signal, a voltage level of the read strobe signal, a difference between a first read strobe signal and a second read strobe signal, or any combination thereof. In some examples, a host device may identify a fault type (e.g., recoverable or unrecoverable) based on a fault signature associated with a given characteristic of the read strobe signal. The host device may perform recovery operations based on the fault type identified.

Abstract: Methods, systems, and devices for memory operations are described. A read command may be received at a memory device from a host device. As part of an error control operation, a first set of error control bits may be generated for the set of data. Based on the first set of error control bits, a failure of a matching operation associated with the error control operation may be determined. Based on determining the failure of the matching operation, a second set of error control bits that is different than the first set of error control bits may be transmitted to the host device. The second set of error control bits may indicate that the matching operation failed at the memory device.

Abstract: Methods, systems, and devices for adaptive user defined health indications are described. A host device may be configured to dynamically indicate adaptive health flags for monitoring health and wear information for a memory device. The host device may indicate, to a memory device, a first index. The first index may correspond to a first level of wear of a set of multiple indexed levels of wear for the memory device. The memory device may determine that a metric of the memory device satisfies the first level of wear and indicate, to the host device, that the first level of wear is satisfied. The host device may receive the indication that the first level of wear is satisfied and indicate, to the memory device, a second level of wear of the set of indexed levels of wear that is different than the first level of wear.

Abstract: Implementations described herein relate to enabling or disabling on-die error-correcting code for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, whether the memory built-in self-test is to be performed with on-die error-correcting code (ECC) disabled or with on-die ECC enabled. The memory device may perform the memory built-in self-test, and selectively test for one or more single-bit errors, based on identifying whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled.

Abstract: Methods, systems, and devices for bit retiring to mitigate bit errors are described. A memory device may retrieve a set of bits from a first row of an address space and may determine that the set of bits includes one or more errors. The memory device may remap at least a portion of the first row from a first row index to a second row index, where the second row index, before the remapping, corresponds to a second row within the address space addressable by the host device. Additionally or alternatively, the memory device may receive a first command to access a first logical address of a memory array that is associated with a first row index. The memory device may determine that the first row includes one or more errors and may transmit a signal indicating that the first row includes the one or more errors.

Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may receive an access command transmitted to the memory device via a bus. The memory device may transmit data requested by the access command over data lines and a control signal that indicates the bus is in an active state over a control line. The control signal may be transmitted during a first unit interval of a read operation. The control signal may be configured to have a first voltage when the bus is in an idle state and a second voltage when the bus is in the active state. The control line may be configured to have or trend toward the first voltage when the bus is in the idle state.

Abstract: Methods, systems, and devices for temperature monitoring for memory devices are described for monitoring one or more temperature ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more temperature ranges. The memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. The indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. The host device may use information included in the indication to perform an operation associated with the memory device.

Abstract: Implementations described herein relate to indicating a status of the memory built-in self-test for multiple memory device ranks. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify a first data mask inversion (DMI) bit of the memory device that is associated with a first rank of the memory device and a second DMI bit of the memory device that is associated with a second rank of the memory device. The memory device may set the first DMI bit to a first value based on determining to perform the memory built-in self-test for the first rank of the memory device. The memory device may perform the memory built-in self-test for the first rank of the memory device based on setting the first DMI bit to the first value.

Abstract: Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.

Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may fail to receive or decode (e.g., successfully receive or successfully decode) an access command transmitted to the memory device via a bus. The bus may enter or remain in an idle state which may cause indeterminate signals to develop on the idle bus. A host device may obtain the indeterminate signals from the idle bus and determine that the indeterminate signals include an error based on a signal that develops on a control line of the idle bus. The signal may be associated with a control signal that indicates errors in a data signal when the control signal has a first voltage, and the control line may be configured to have the first voltage when the bus is idle.

Abstract: Methods, systems, and devices for evaluation of memory device health monitoring logic are described. For example, a memory device may include health monitoring logic operable to activate certain internal health monitors of a set of multiple monitors and to communicate an output associated with the activated monitors. In a first mode of operation, the health monitoring logic may provide a single output that is generated from multiple outputs of the set of monitors. In a second mode of operation, the health monitoring logic may cycle through certain monitors (e.g., in a test mode), and may generate an output corresponding to respective active monitors as it cycles through the set of monitors. The health monitoring logic may communicate an output specific to each monitor to a host device such that the host device may evaluate an output from each monitor of the set of monitors.

Abstract: Implementations described herein relate to interrupting a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is to be interrupted while the memory built-in self-test is being performed using a test mode. The memory device may be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode but may not be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using a repair mode. The memory device may interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode.