Patents by Inventor Scott E. Schaefer

Scott E. Schaefer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11054995
    Abstract: Methods, systems, and devices for row hammer protection for a memory device are described. A memory device may identify a threshold of related row accesses (e.g., access commands or activates to a same row address or a row address space) for a memory array. In a first operation mode, the memory device may execute commands received from a host device on the memory array. The memory device may determine that a metric of the received row access commands satisfies the threshold of related row accesses. The memory device may switch the memory array from the first operation mode to a second operation mode based on satisfying the threshold. The second operation mode may restrict access to at least one row of the memory, while the first mode may be less restrictive. Additionally or alternatively, the memory device may notify the host device that the metric has satisfied the threshold.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Publication number: 20210191660
    Abstract: Methods, systems, and devices for address verification for a memory device are described. When a memory device receives a write command, the memory device may store, in association with the data written, an indication of a write address associated with the write command. When the memory device receives a read command, the memory device may retrieve data and a previously stored write address associated with the retrieved data, and the memory device may verify a read address associated with the read command against the previously stored write address associated with retrieved data. Thus, for example, the memory device may verify whether data read from the memory array based on an address associated with a read command is data that, when previously written to the memory array, was written in response to a write command associated with a matching address.
    Type: Application
    Filed: November 13, 2020
    Publication date: June 24, 2021
    Inventors: Aaron P. Boehm, Scott E. Schaefer
  • Publication number: 20210173562
    Abstract: Methods, systems, and devices for reset verification in a memory system are described. In some examples, a memory device may perform a reset operation and set a mode register to a first value based on performing the reset operation. The first value may be associated with a successful execution of the reset command. The memory device may transmit an indication to a host device based on determining the first value. The host device may determine from the received indication or from the first value stored in the mode register that the first value is associated with the successful execution of the reset command. Thus, the memory device, or the host device, or both may be configured to verify whether the reset operation is successful.
    Type: Application
    Filed: November 13, 2020
    Publication date: June 10, 2021
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Publication number: 20210157494
    Abstract: Methods, systems, and devices for refresh counters in a memory system are described. In some examples, a memory device may include two or more counters configured to increment a respective count based on refresh operations performed on a memory array. A comparison may be made between two or more of the respective counts, which may include determining a difference between the respective counts or a difference in rate of incrementing. A memory device may transmit an indication to a host device based on determining a difference between counters, and the memory device, the host device, or both, may perform various operations or enter various operational modes based on the determined difference.
    Type: Application
    Filed: November 5, 2020
    Publication date: May 27, 2021
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Patent number: 10983934
    Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Matthew A. Prather
  • Publication number: 20210049068
    Abstract: Methods, systems, and devices for coordinated error correction are described. A memory device may indicate, for example to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. After performing the comparison, an indication of or based on whether the compared error correction codes match may be provided to the external device. The external device may use the indication to detect errors in the received version of the data, or to manage data storage in the memory device, or both, among other operations.
    Type: Application
    Filed: July 28, 2020
    Publication date: February 18, 2021
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Publication number: 20200394103
    Abstract: Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 17, 2020
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Publication number: 20200371873
    Abstract: Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.
    Type: Application
    Filed: April 24, 2020
    Publication date: November 26, 2020
    Inventors: Scott E. Schaefer, Aaron P. Boehrn
  • Publication number: 20200349097
    Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Inventors: Scott E. Schaefer, Matthew A. Prather
  • Publication number: 20200341847
    Abstract: Methods, systems, and devices for performing safety event detection for a memory device are described. For example, a memory array of a memory device may operate in a first mode of operation (e.g., a normal mode of operation). An event associated with a reduction of data integrity for the memory array may be detected. In some cases, the event may be associated with a temperature of the memory device, a voltage level detected at the memory device, an error event at the memory device, or the like. Based on the detected event, it may be determined whether to adjust the operation of the memory device to a second mode of operation (e.g., a safe mode of operation). The second mode of operation may correspond to a mode of operation that increases data retention characteristics.
    Type: Application
    Filed: April 3, 2020
    Publication date: October 29, 2020
    Inventors: Aaron P. Boehm, Scott E. Schaefer
  • Publication number: 20200278908
    Abstract: Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 3, 2020
    Inventors: Scott E. Schaefer, Jongtae Kwak, Aaron P. Boehm
  • Patent number: 10754801
    Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Matthew A. Prather
  • Publication number: 20200264950
    Abstract: Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.
    Type: Application
    Filed: February 17, 2020
    Publication date: August 20, 2020
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Publication number: 20200258566
    Abstract: Methods, systems, and devices for refresh rate management for a memory device are described. A memory device may receive refresh commands for a memory array (e.g., from a host device). The memory device may determine that a refresh rate associated with the refresh commands is below a threshold, and the threshold may be based on a condition of the memory array. The memory device may transmit signaling (e.g., to a host device) indicating that the refresh rate associated with the refresh commands is below the threshold. Additionally or alternatively, the memory device may switch from a first mode of operation to a second mode of operation based on determining that the refresh rate associated with the refresh commands is below the threshold. The second mode of operation may restrict access to at least a portion of the memory array. Additionally or alternatively, the second mode of operation may include a self-refresh mode.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 13, 2020
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Publication number: 20200258565
    Abstract: Methods, systems, and devices for refresh rate control for a memory device are described. For example, a memory array of a memory device may be refreshed according to a first set of refresh parameters, such as a refresh rate. The memory device may detect an event at the memory device associated with a reduction in data integrity. In some cases, the event may be associated with a temperature of the memory device, a voltage level detected at the memory device, an error event at the memory device, or the like. As a result of detecting the event, the memory device may adapt one or more of the set of refresh parameters, such as increasing the refresh rate for the memory array. In some cases, the memory device may adapt the set of refresh parameters by increasing a quantity of rows of the memory array that are refreshed during a refresh operation, decreasing a periodicity between refresh operations, or both.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 13, 2020
    Inventors: Scott E. Schaefer, Aaron p. Boehm
  • Publication number: 20200242057
    Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Inventors: Scott E. Schaefer, Matthew A. Prather
  • Patent number: 10657081
    Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Matthew A. Prather
  • Publication number: 20200117392
    Abstract: Methods, systems, and devices for performing memory command verification are described. A system may include a memory device and a memory controller, which may be external (e.g., a host device). The memory device may receive, from the memory controller, a command indicating a type of operation and an address. The memory device may decode the command and execute an operation (e.g., the operation corresponding to the decoded command) at an execution location on the memory device. The system (e.g., the memory device or the memory controller) may determine whether the executed operation and execution location match the type of operation and address indicated in the command, and the system may thereby determine an error associated with the decoding, the execution, or both of the command.
    Type: Application
    Filed: September 23, 2019
    Publication date: April 16, 2020
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Publication number: 20200117393
    Abstract: Methods, systems, and devices for command block management are described. A memory device may receive a command (e.g., from a host device). The memory device may determine whether the command is defined by determining if the command is included within a set of defined commands. In the case that a received command is absent from the set of defined commands (e.g., the command is undefined), the memory device may block the command from being decoded for execution by the memory device. In some cases, the memory device may switch from a first operation mode to a second operation mode based on receiving an undefined command. The second operation mode may restrict an operation of the memory device, while the first mode may be less restrictive, in some cases. Additionally or alternatively, the memory device may indicate the undefined command to another device (e.g., the host device).
    Type: Application
    Filed: September 23, 2019
    Publication date: April 16, 2020
    Inventors: Aaron P. Boehm, Scott E. Schaefer
  • Publication number: 20200117537
    Abstract: Methods, systems, and devices are described herein for using codewords to detect or correct errors in data (e.g., data stored in a memory device). A host device may generate one or more codewords associated with data to be stored in the memory device. In some cases, the host device may generate one or more codewords for error detection and correction (e.g., corresponding to data transmitted by the host device to the memory device). In some cases, the host device may transmit the codewords and the associated data using an extended (e.g., adjustable) burst length such that the one or more codewords may be included in the burst along with the data. Additionally or alternatively, the host device may transmit one or more of the codewords over one or more channels different than the one or more channels used to transmit the data.
    Type: Application
    Filed: September 23, 2019
    Publication date: April 16, 2020
    Inventors: Scott E. Schaefer, Aaron P. Boehm