Patents by Inventor Scott E. Schaefer

Scott E. Schaefer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220342604
    Abstract: Methods, systems, and devices for memory device health evaluation at a host device are described. The health evaluation relates to a host device that is associated with a memory device that monitors and reports health information, such as one or more parameters associated with a status of the memory device. The memory device may transmit the health information to the host device, which may perform one or more operations and may transmit the health information to a device of another entity of a system (e.g., ecosystem) including the host device. The host device may include one or more circuits for transmitting and processing the health information, such as a system health engine, a safety engine, a communication component, or a combination thereof. Based on a determination by the host device or information received from an external device, the host device may transmit a command to the memory device.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 27, 2022
    Inventors: Aaron P. Boehm, Mark D. Ingram, Scott E. Schaefer, Scott D. Van De Graaff, Todd J. Plum
  • Patent number: 11474698
    Abstract: Methods, systems, and devices for reset verification in a memory system are described. In some examples, a memory device may perform a reset operation and set a mode register to a first value based on performing the reset operation. The first value may be associated with a successful execution of the reset command. The memory device may transmit an indication to a host device based on determining the first value. The host device may determine from the received indication or from the first value stored in the mode register that the first value is associated with the successful execution of the reset command. Thus, the memory device, or the host device, or both may be configured to verify whether the reset operation is successful.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Publication number: 20220317916
    Abstract: Methods, systems, and devices for inter-device communications for memory health monitoring are described. These communications relate to a host device that is associated with a memory device that monitors and reports health information (e.g., one or more parameters associated with a status of the memory device). The memory device may transmit the health information to the host device (e.g., a vehicle or a computer of the vehicle), which may perform one or more operations and transmit the health information to another entity of a system (e.g., ecosystem) including the host device. The host device may additionally or alternatively use the health information. In some cases, the other entity may receive the health information and transmit a signal back to the host device based on the health information. The other entity of the ecosystem may receive the health information and may make a determination based on the health information.
    Type: Application
    Filed: March 15, 2022
    Publication date: October 6, 2022
    Inventors: Aaron P. Boehm, Mark D. Ingram, Scott E. Schaefer, Scott D. Van De Graaff, Todd J. Plum
  • Patent number: 11436169
    Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Matthew A. Prather
  • Patent number: 11436082
    Abstract: Methods, systems, and devices for internal error correction for memory devices are described. A memory device may perform a read operation at a memory array having a data partition and an error check partition and may obtain a first set of bits from the data partition and a second set of bits from the error check partition. The memory device may determine a first error detection result based on a value of a determined syndrome. The memory device may obtain a parity bit from the first set of bits and determine a second error detection result based on a comparison of the parity bit with a second function of the subset of the first set of bits. The memory device may transmit the first set of bits to a host device based at least in part on the first and second error detection results.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Aaron P. Boehm, Scott E. Schaefer
  • Publication number: 20220238174
    Abstract: Methods, systems, and devices for metadata storage at a memory device are described to support storage of metadata information and error control information at a memory device. The metadata information and error control information may be received at the memory device via a sideband channel and corresponding pin. For example, a set of bits received via the pin may include a subset of error control bits and a subset of metadata bits. Circuitry at the memory device may receive the set of bits via the pin and may identify metadata information and error control information within the set of bits. The circuitry may route the metadata information to a corresponding subset of memory cells and the error control information to an error control circuit, where the error control circuit may route the error control information to a corresponding subset of memory cells.
    Type: Application
    Filed: January 19, 2022
    Publication date: July 28, 2022
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Publication number: 20220237081
    Abstract: Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.
    Type: Application
    Filed: April 15, 2022
    Publication date: July 28, 2022
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Publication number: 20220238175
    Abstract: Methods, systems, and devices for bit retiring to mitigate bit errors are described. A memory device may retrieve a set of bits from a first row of an address space and may determine that the set of bits includes one or more errors. The memory device may remap at least a portion of the first row from a first row index to a second row index, where the second row index, before the remapping, corresponds to a second row within the address space addressable by the host device. Additionally or alternatively, the memory device may receive a first command to access a first logical address of a memory array that is associated with a first row index. The memory device may determine that the first row includes one or more errors and may transmit a signal indicating that the first row includes the one or more errors.
    Type: Application
    Filed: January 20, 2022
    Publication date: July 28, 2022
    Inventor: Scott E. Schaefer
  • Publication number: 20220197745
    Abstract: Methods, systems, and devices for coordinated error correction are described. A memory device may indicate, for example to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. After performing the comparison, an indication of or based on whether the compared error correction codes match may be provided to the external device. The external device may use the indication to detect errors in the received version of the data, or to manage data storage in the memory device, or both, among other operations.
    Type: Application
    Filed: March 9, 2022
    Publication date: June 23, 2022
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Publication number: 20220188186
    Abstract: Methods, systems, and devices are described herein for using codewords to detect or correct errors in data (e.g., data stored in a memory device). A host device may generate one or more codewords associated with data to be stored in the memory device. In some cases, the host device may generate one or more codewords for error detection and correction (e.g., corresponding to data transmitted by the host device to the memory device). In some cases, the host device may transmit the codewords and the associated data using an extended (e.g., adjustable) burst length such that the one or more codewords may be included in the burst along with the data. Additionally or alternatively, the host device may transmit one or more of the codewords over one or more channels different than the one or more channels used to transmit the data.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 16, 2022
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Patent number: 11334435
    Abstract: Methods, systems, and devices for performing safety event detection for a memory device are described. For example, a memory array of a memory device may operate in a first mode of operation (e.g., a normal mode of operation). An event associated with a reduction of data integrity for the memory array may be detected. In some cases, the event may be associated with a temperature of the memory device, a voltage level detected at the memory device, an error event at the memory device, or the like. Based on the detected event, it may be determined whether to adjust the operation of the memory device to a second mode of operation (e.g., a safe mode of operation). The second mode of operation may correspond to a mode of operation that increases data retention characteristics.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Aaron P. Boehm, Scott E. Schaefer
  • Publication number: 20220147419
    Abstract: Methods, systems, and devices for targeted command/address parity low lift are described. A memory device may receive a command (e.g., a write command or a read command) from a host device over a first set of pins and may perform data transfer over a second set of pins with the host device during a set of time intervals according to the command. The memory device may exchange a parity bit associated with the command with the host device over a third set of pins during a first time intervals of the set of time intervals. In some cases, the third memory device may exchange at least one additional bit associated with the command with the host device during at least one time interval of the set of time intervals.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 12, 2022
    Inventors: Aaron P. Boehm, Scott E. Schaefer
  • Publication number: 20220137827
    Abstract: Methods, systems, and devices for life expectancy monitoring for memory devices are described. A memory device may monitor a parameter of a component of the memory device or the memory device overall, and may determine whether the parameter satisfies a threshold. The parameter may represent or be associated with a lifetime of the component, a level of wear of the component, or an operating parameter violation of the component, or any combination thereof. The memory device may communicate, to a host device, an indication of the parameter satisfying the threshold, and the host device may use the information in the indication to adjust one or more parameters associated with operating the memory device, among other example operations.
    Type: Application
    Filed: October 19, 2021
    Publication date: May 5, 2022
    Inventors: Scott E. Schaefer, Aaron P. Boehm, Scott Van De Graaff, Todd Jackson Plum, Mark D. Ingram
  • Publication number: 20220139487
    Abstract: Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may fail to receive or decode (e.g., successfully receive or successfully decode) an access command transmitted to the memory device via a bus. The bus may enter or remain in an idle state which may cause indeterminate signals to develop on the idle bus. A host device may obtain the indeterminate signals from the idle bus and determine that the indeterminate signals include an error based on a signal that develops on a control line of the idle bus. The signal may be associated with a control signal that indicates errors in a data signal when the control signal has a first voltage, and the control line may be configured to have the first voltage when the bus is idle.
    Type: Application
    Filed: October 15, 2021
    Publication date: May 5, 2022
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Publication number: 20220137880
    Abstract: Methods, systems, and devices for memory bus drive defect detection and related operations are described. A controller coupled with a memory array may receive a command for data. The memory array may include one or more pins for communicating data to and from the memory array, in response to the command. The controller may transmit to the memory array, over a bus that is coupled with the controller and the pins, the command. The controller may detect, based at least in part on a resistor coupled with the bus and a power supply of the memory array, that the bus is operating in a first state after transmitting the command. The first state may comprise a voltage that is relatively higher than a voltage of the second state. The controller may determine a defect associated with the bus or the pin based on detecting the bus in the first state.
    Type: Application
    Filed: October 19, 2021
    Publication date: May 5, 2022
    Inventors: Scott E. Schaefer, Melissa I. Uribe
  • Patent number: 11307929
    Abstract: Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Patent number: 11294766
    Abstract: Methods, systems, and devices for coordinated error correction are described. A memory device indicates, to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. Based on a result of the comparison, an indication of whether the compared error correction codes match is provided to the external device. The external device uses the indication to detect errors in the received version of the data, to manage data storage in the memory device, or both.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Publication number: 20220100428
    Abstract: Methods, systems, and devices for operating frequency monitoring for memory devices are described for monitoring one or more operating frequency ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more operating frequency ranges. The memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. The indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. The host device may use information included in the indication to perform an operation associated with the memory device.
    Type: Application
    Filed: September 1, 2021
    Publication date: March 31, 2022
    Inventors: Aaron P. Boehm, Todd Jackson Plum, Scott D. Van De Graaff, Scott E. Schaefer, Mark D. Ingram
  • Publication number: 20220075532
    Abstract: Methods, systems, and devices for selectable error control for memory device are described. An apparatus may include a memory array and a circuit configurable to perform a first error control operation and a second error control operation on data stored by the memory array. The circuit may include a first plurality of gates enabled during the first error control operation and configured to generate a first set of bits associated with a first matrix of the first error control operation. The circuit may also include a second plurality of gates enabled during the second error control operation and configured to generate a second set of bits associated with the second matrix of the second error control operation. The circuit may further include a third plurality of gates configured to generate a third set of bits that are common to both the first matrix and the second matrix.
    Type: Application
    Filed: August 2, 2021
    Publication date: March 10, 2022
    Inventor: Scott E. Schaefer
  • Publication number: 20220066701
    Abstract: Methods, systems, and devices for performing memory command verification are described. A system may include a memory device and a memory controller, which may be external (e.g., a host device). The memory device may receive, from the memory controller, a command indicating a type of operation and an address. The memory device may decode the command and execute an operation (e.g., the operation corresponding to the decoded command) at an execution location on the memory device. The system (e.g., the memory device or the memory controller) may determine whether the executed operation and execution location match the type of operation and address indicated in the command, and the system may thereby determine an error associated with the decoding, the execution, or both of the command.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 3, 2022
    Inventors: Scott E. Schaefer, Aaron P. Boehm