Abstract: A mechanism for accurate alignment of semiconductor package back side interconnect processing is provided. As semiconductor die are placed in position for an encapsulated panel, two or more alignment die having fiducial markings formed on the back, or non-active, side of those die are also placed in the panel. Once all the die and other components have been placed for the panel, the panel is encapsulated using an encapsulant. Excess encapsulant, if any, is removed by a process such as backgrinding. The back grinding process exposes the back side of the alignment die and the fiducial features on those alignment die. The fiducial features on the alignment die can then be used for alignment of backside processing operations on the panel.

Abstract: A method for forming through vias in a semiconductor device package prior to package encapsulation is provided. One or more signal conduits are formed through photolithography and metal deposition on a printed circuit substrate having interconnect pads. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die, wire bonding, and other parts of the package. Free ends of each signal conduit are exposed and the signal conduits are used as through vias to provide signal-bearing pathways between connections from a top-mounted package to a printed circuit substrate interconnect and electrical contacts of the semiconductor die or package contacts. Using this method, signal conduits can be provided in a variety of geometric placings on the printed circuit substrate for inclusion in a semiconductor device package. A semiconductor device package incorporating the pre-fabricated through vias is also provided.

Abstract: A method for fabricating a thin package that encapsulates a capped MEMS device electrically coupled with one or more encapsulated semiconductor devices is provided. A wafer-level packaging methodology is used in which the capped MEMS device is electrically coupled to a package interconnect, which then allows for electrical coupling to the one or more encapsulated semiconductor devices, as well as external connections.

Abstract: A semiconductor device package having an embedded three-dimensional interconnect structure and a process for making such a package is provided. One or more ball conductors are attached to a major surface of a substrate that provides at least an electrical conduit from the ball conductor to an opposite major surface of the substrate. The substrate can also provide an interconnect between solder balls. The combination of solder balls and substrate is encapsulated in the semiconductor device package. The ends of the signal conduits are exposed on one major surface of the device package, while a portion of the ball conductors is exposed on the opposite major surface of the device package. The ball conductors and signal conduits provide signal-bearing pathways between the major surfaces of the package. Contacts created by the back grinded ball conductors are used to form a package-on-package structure by coupling with contacts from another package.

Abstract: A method for forming through vias in a semiconductor device package prior to package encapsulation is provided. One or more signal conduits are formed through photolithography and metal deposition on a printed circuit substrate having interconnect pads. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die, wire bonding, and other parts of the package. Free ends of each signal conduit are exposed and the signal conduits are used as through vias to provide signal-bearing pathways between connections from a top-mounted package to a printed circuit substrate interconnect and electrical contacts of the semiconductor die or package contacts. Using this method, signal conduits can be provided in a variety of geometric placings on the printed circuit substrate for inclusion in a semiconductor device package. A semiconductor device package incorporating the pre-fabricated through vias is also provided.

Abstract: A method for fabricating a thin package that encapsulates a capped MEMS device electrically coupled with one or more encapsulated semiconductor devices is provided. A wafer-level packaging methodology is used in which the capped MEMS device is electrically coupled to a package interconnect, which then allows for electrical coupling to the one or more encapsulated semiconductor devices, as well as external connections.

Abstract: A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are coupled to a lead frame that is subsequently embedded in an encapsulated semiconductor device package. The free end of signal conduits is exposed while the other end remains coupled to a lead frame. The signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package and the leads.

Abstract: A mechanism for accurate alignment of semiconductor package back side interconnect processing is provided. As semiconductor die are placed in position for an encapsulated panel, two or more alignment die having fiducial markings formed on the back, or non-active, side of those die are also placed in the panel. Once all the die and other components have been placed for the panel, the panel is encapsulated using an encapsulant. Excess encapsulant, if any, is removed by a process such as backgrinding. The back grinding process exposes the back side of the alignment die and the fiducial features on those alignment die. The fiducial features on the alignment die can then be used for alignment of backside processing operations on the panel.

Abstract: A method for forming signal conduits before encapsulation for incorporation as through vias in a semiconductor device package is provided. One or more signal conduits are formed through photolithography and metal deposition on a metal film or substrate. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die and other parts of the package. The ends of the signal conduits are exposed and the signal conduits can then be used as through vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package, and electrical contacts of the semiconductor die. Using this method, signal conduits can be provided in a variety of geometric placings in the semiconductor device package. A semiconductor device package including the signal conduits made from the above method is also provided.

Abstract: A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications.

Abstract: A semiconductor device includes a first cap wafer having a first opening extending through the first cap wafer, and a second cap wafer bonded to the first cap wafer, wherein the second cap wafer has a second opening extending through the second cap wafer, and wherein the first opening is misaligned with respect to the second opening. The second cap wafer is bonded to a device wafer, wherein a cavity is formed between the device wafer and the second cap wafer, and wherein the device wafer comprises at least one semiconductor device in the cavity. A vacuum sealing layer is formed over the first cap wafer, wherein the sealing layer vacuum seals the first opening.

Abstract: A method for fabricating a semiconductor package is disclosed that includes providing a supply of lead elements, mounting a plurality of the lead elements on a lead frame until a predetermined number of lead elements are placed on the lead frame, and connecting other components on the lead frame to the lead elements.

Abstract: Methods for forming a microelectronic assembly (82) are provided. In one embodiment, the method includes providing a device substrate (50) having a plurality of electronic components (42) coupled thereto, and providing a carrier substrate (54) having first and second opposing surfaces (60, 62) and including a plurality of openings (58) extending between the first and second opposing surfaces (60, 62) and a plurality of depressions (64) formed on the first opposing surface (60). The method further includes attaching the device substrate (50) to the first opposing surface (60) of the carrier substrate (54) using an adhesive material (56) such that at least some of the adhesive material (56) is adjacent to at least some of the plurality of depressions (64), and removing the device substrate (50) from the carrier substrate (54).

Abstract: A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.

Abstract: A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.

Abstract: A semiconductor device includes a first cap wafer having a first opening extending through the first cap wafer, and a second cap wafer bonded to the first cap wafer, wherein the second cap wafer has a second opening extending through the second cap wafer, and wherein the first opening is misaligned with respect to the second opening. The second cap wafer is bonded to a device wafer, wherein a cavity is formed between the device wafer and the second cap wafer, and wherein the device wafer comprises at least one semiconductor device in the cavity. A vacuum sealing layer is formed over the first cap wafer, wherein the sealing layer vacuum seals the first opening.

Abstract: Methods for forming electronic assemblies are provided. A device substrate having a plurality of electronic components embedded therein is provided. The device substrate is attached to a carrier substrate using an adhesive material. A plurality of cuts are formed through the device substrate to divide the device substrate into a plurality of portions. Each of the plurality of portions includes at least one of the electronic components. A force is applied to each of the plurality of portions in a direction away from the carrier substrate to remove the plurality of portions from the carrier substrate.

Abstract: A method for forming a semiconductor device includes providing a first cap wafer having a first opening extending through the first cap wafer, and a second cap wafer bonded to the first cap wafer, wherein the second cap wafer has a second opening extending through the second cap wafer, and wherein the first opening is misaligned with respect to the second opening. After the providing the first cap wafer and second cap wafer, the second cap wafer is bonded to a device wafer, wherein a cavity is formed between the device wafer and the second cap wafer, and wherein the device wafer comprises at least one semiconductor device in the cavity. After the bonding the second cap wafer to the device wafer, a vacuum is applied, wherein during the applying the vacuum, a sealing layer is formed over the first cap wafer, wherein the sealing layer seals the first opening.

Abstract: An integrated conformal electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules (30-33) to a process carrier (1) using a double side adhesive tape (2), and then sequentially depositing an insulating layer (15) and a conductive shielding layer (16) before encapsulating the modules with a molding compound (17). After removing the adhesive tape (2) to expose a surface of the encapsulated modules, a multi-layer circuit substrate (100) is formed over the exposed surface, where the circuit substrate includes shielding via structures (101-112) that are aligned with and electrically connected to the conductive shielding layer (16), thereby encircling and shielding the circuit module(s).

Abstract: A method for mini module EMI shielding effectiveness evaluation comprises providing a test vehicle including at least one test platform. The test platform includes at least one mini emitter, a mini receiver with a reference shield, and a mini receiver with a shield under test. EMI shielding effectiveness transmission signals are applied to the at least one mini emitter. Signals received by the mini receiver with a shield under test and the mini receiver with the reference shield are evaluated. The mini emitter, mini receiver with the reference shield, and mini receiver with the shield under test comprise components fabricated concurrently and under fabrication conditions used for fabrication of the test platform of the test vehicle. As used herein, a mini emitter and mini receiver may be interchanged according to the requirements of a given EMI shielding effectiveness evaluation.