Patents by Inventor Scott R. Summerfelt

Scott R. Summerfelt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5888659
    Abstract: The invention forms improved ferroelectric (or pyroelectric) material by doping an intrinsic perovskite material having an intrinsic ferroelectric (or pyroelectric) critical grain size with one or more donor dopants, then forming a layer of the donor doped perovskite material having an average grain size less than the intrinsic ferroelectric (or pyroelectric) critical gran size whereby the remanent polarization (or pyroelectric figure of merit) of the layer is substantially greater than the remanent polarization (or pyroelectric figure of merit) of the intrinsic perovskite material with an average grain size similar to the average grain size of the layer. The critical ferroelectric (or pyroelectric) grain size, as used herein, means the largest grain size such that the remanent polarization (or pyroelectric figure of merit) starts to rapidly decrease with decreasing grain sizes.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 30, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Howard R. Beratan, Bernard M. Kulwicki
  • Patent number: 5851896
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), a conductive exotic-nitride barrier layer (e.g. Ti--Al--N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the exotic-nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The exotic-nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 22, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 5825055
    Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a germanium layer 28 directly or indirectly on a semiconductor substrate 20; and depositing a high-dielectric constant oxide 32 (e.g. a ferroelectric oxide) on the germanium layer. Preferably, the germanium layer is epitaxially grown on the semiconductor substrate. This is also a semiconductor structure, comprising: a semiconductor substrate; a germanium layer on the semiconductor substrate; and a high-dielectric constant oxide on the germanium layer. Preferably the germanium layer is single-crystal. Preferably the substrate is silicon and the germanium layer is less than about 1 nm thick or the substrate is gallium arsenide (in which case the thickness of the germanium layer is not as important). A second germanium layer 40 may be grown on top of the high-dielectric constant oxide and a conducting layer 42 (possibly epitaxial) grown on the second germanium layer.
    Type: Grant
    Filed: January 3, 1997
    Date of Patent: October 20, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 5811851
    Abstract: Generally, according to the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material. One embodiment of the present invention is a microelectronic structure comprising a supporting layer having a principal surface, and an adhesion layer overlying the principal surface of the supporting layer, wherein the adhesion layer comprises a top surface and an expanded, oxidized sidewall (e.g. TiO.sub.2 40).
    Type: Grant
    Filed: June 11, 1996
    Date of Patent: September 22, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Yasushiro Nishioka, Scott R. Summerfelt, Kyung-ho Park, Pijush Bhattacharya
  • Patent number: 5792377
    Abstract: An array of thermal sensitive elements (16) may be formed from a pyroelectric substrate (46) having an infrared absorber and common electrode assembly (18) attached thereto. A first layer of electrically conductive contacts (60) is formed to define in part masked (61) and unmasked (68) regions of the substrate (46). A second layer of electrically conductive contacts (62) may be formed on the first layer of contacts (60). A mask layer (66) is formed to encapsulate the exposed portions of the second layer of contacts (62). The unmasked regions (68) are exposed to an etchant (70) and irradiated to substantially increase the reactivity between the unmasked regions (68) and the etchant (70) such that during irradiation, the etchant (70) removes the unmasked regions (68) substantially faster than the first layer of contacts (60) and the mask layer (66).
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: August 11, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Howard R. Beratan, Scott R. Summerfelt
  • Patent number: 5793057
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an amorphous nitride barrier layer (e.g. Ti--Si--N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the amorphous nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The amorphous nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 11, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 5781404
    Abstract: A preferred embodiment of this invention comprises a first thin dielectric buffer layer of a first leakage-current-density material (e.g. strontium titanate 32) with a first moderate-dielectric-constant, a high-dielectric-constant layer of a second leakage-current-density material (e.g. barium strontium titanate 34) overlaying the first thin dielectric buffer layer, and a second thin dielectric buffer layer of a third leakage-current-density material (e.g. strontium titanate 36) with a second moderate-dielectric-constant overlaying the high-dielectric-constant layer, wherein the first and third leakage-current-density materials have substantially lower leakage-current-densities than the second leakage-current-density material. The first and second thin moderate-dielectric-constant buffer layers (e.g. strontium titanate 32, 36) substantially limit the leakage-current-density of the structure, with only modest degradation of the dielectric constant of the structure.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 14, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Howard Roy Beratan
  • Patent number: 5746930
    Abstract: An array of thermal sensitive elements (16) may be formed from a pyroelectric substrate (46) having an infrared absorber and common electrode assembly (18) attached thereto. A first layer of electrically conductive contacts (60) is formed to define in part masked (61) and unmasked (68) regions of the substrate (46). A second layer of electrically conductive contacts (62) may be formed on the first layer of contacts (60). A mask layer (66) is formed to encapsulate the exposed portions of the second layer of contacts (62). The unmasked regions (68) are exposed to an etchant (70) and irradiated to substantially increase the reactivity between the unmasked regions (68) and the etchant (70) such that during irradiation, the etchant (70) removes the unmasked regions (68) substantially faster than the first layer of contacts (60) and the mask layer (66).
    Type: Grant
    Filed: January 3, 1995
    Date of Patent: May 5, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Howard R. Beratan, Scott R. Summerfelt
  • Patent number: 5729054
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an noble-metal-insulator-alloy barrier layer (e.g. Pd-Si-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the noble-metal-insulator-alloy layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The noble-metal-insulator-alloy barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 17, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Jason Reid, Marc Nicolet, Elzbieta Kolawa
  • Patent number: 5721043
    Abstract: The invention described is an improved dielectric material formed as a film on the surface of a substrate by adding lead to an original perovskite material having an original critical grain size to form a lead enhanced perovskite material, then forming a layer of the lead enhanced perovskite material having an average grain size less than the original critical grain size whereby the dielectric constant of the layer is substantially greater than the dielectric constant of the original perovskite material with an average grain size similar to the average grain size of the layer. The critical grain size, as used herein, means the largest grain size such that the dielectric constant starts to rapidly decrease with decreasing grain sizes. Preferably, the lead enhanced perovskite material is further doped with one or more acceptor dopants whereby the resistivity is substantially increased and/or the loss tangent is substantially decreased. Preferably, the original perovskite material has a chemical composition ABO.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: February 24, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Howard R. Beratan, Bernard M. Kulwicki
  • Patent number: 5696018
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an noble-metal-insulator-alloy barrier layer (e.g. Pd-Si-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the noble-metal-insulator-alloy layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The noble-metal-insulator-alloy barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 9, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Jason Reid, Marc Nicolet, Elzbieta Kolawa
  • Patent number: 5679980
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), a conductive exotic-nitride barrier layer (e.g. Ti-Al-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the exotic-nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The exotic-nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: October 21, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 5665628
    Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an amorphous nitride barrier layer (e.g. Ti--Si--N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the amorphous nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The amorphous nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 9, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 5656852
    Abstract: Generally, the present invention utilizes a lower electrode comprising a sidewall spacer to fore a top surface with rounded comers on which HDC material can be deposited without substantial cracking. An important aspect of the present invention is that the sidewall spacer does not reduce the electrical contact surface area between the lower electrode and the HDC material layer as compared to a similar structure containing a lower electrode without a sidewall spacer. One embodiment of the present invention is a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises an adhesion layer (e.g TiN 36), an unreactive layer (e.g. Pt 42), a sidewall spacer (e.g. SiO.sub.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 12, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Yasushiro Nishioka, Scott R. Summerfelt, Kyung-ho Park, Pijush Bhattacharya
  • Patent number: 5654580
    Abstract: An etching process is provided using electromagnetic radiation and a selected etchant (52) to selectively remove various types of materials (53) from a substrate (48). Contacts (49, 56, 64) may be formed to shield the masked regions (51) of the substrate (48) having an attached coating (20) during irradiation of the unmasked regions (53) of the substrate (48). The unmasked regions (53) are then exposed to an etchant (52) and irradiated to substantially increase their reactivity with the etchant (52) such that the etchant (52) etches the unmasked regions (53) substantially faster than the masked regions (51) and the contacts (49, 56, 64).
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: August 5, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Howard R. Beratan, James F. Belcher, Scott R. Summerfelt
  • Patent number: 5650646
    Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a buffer layer of non-Pb/Bi-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate; and depositing a Pb/Bi-containing high-dielectric constant oxide on the buffer layer. Alternately this may be a structure useful in semiconductor circuitry, comprising: a buffer layer 26 of non-lead-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate 10; and a lead-containing high-dielectric constant oxide 28 on the buffer layer. Preferably a germanium layer 12 is epitaxially grown on the semiconductor substrate and the buffer layer is grown on the germanium layer. When the substrate is silicon, the non-Pb/Bi-containing high-dielectric constant oxide layer is preferably less than about 10 nm thick.
    Type: Grant
    Filed: February 27, 1995
    Date of Patent: July 22, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 5647946
    Abstract: An array of thermal sensor elements (16) is formed from a pyroelectric substrate (46) having an infrared absorber and common electrode assembly (18) attached thereto. A first layer of metal contacts (60) is formed to define masked (61) and unmasked (68) regions of the substrate (46). A second layer of metal contacts (62) is formed on the first layer of contacts (60). A radiation etch mask layer (66) is formed to encapsulate the exposed portions of the second layer of contacts (62). A dry-etch mask layer (74) is formed to encapsulate the exposed portions of the first layer of contacts (60) and radiation etch mask layer (66). An initial portion of each unmasked region (68) is etched using a dry-etch process. The remaining portions of the unmasked regions (68) are exposed to an etchant (70) and irradiated with electromagnetic energy to substantially increase the reactivity between the remaining portions and the etchant (70).
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: July 15, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: James F. Belcher, Howard R. Beratan, Scott R. Summerfelt
  • Patent number: 5643033
    Abstract: An anode plate 50 for use in a field emission flat panel display device comprises a transparent planar substrate 58 having a plurality of electrically conductive, parallel stripes 52 comprising the anode electrode of the device, which are covered by phosphors 54.sub.R, 54.sub.G and 54.sub.B. A substantially opaque, electrically insulating material 56 is affixed to substrate 58 in the spaces between conductors 52, acting as a barrier to the passage of ambient light into and out of the device. The electrical insulating quality of opaque material 56 increases the electrical isolation of conductive stripes 52 from one another, reducing the risk of breakdown due to increased leakage current. Opaque material 56 preferably comprises glass having impurities dispersed therein, wherein the impurities may include one or more organic dyes, selected to provide relatively uniform opacity over the visible range of the electromagnetic spectrum.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 1, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Bruce E. Gnade, Daron G. Evans, Scott R. Summerfelt, Jules D. Levine
  • Patent number: 5638599
    Abstract: Thermal isolation mesas 36 comprising a porous material 64 are used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous material 64 is preferably a silicon-dioxide xerogel. The mesas 36 may also comprise a protective film 66.
    Type: Grant
    Filed: March 29, 1995
    Date of Patent: June 17, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Howard R. Beratan, Chih-Chen Cho, Scott R. Summerfelt
  • Patent number: 5626906
    Abstract: A preferred embodiment of this invention comprises a perovskite-seed layer (e.g. calcium ruthenate 40) between a conductive oxide layer (e.g. ruthenium oxide 36) and a perovskite dielectric material (e.g. barium strontium titanate 42), wherein the perovskite-seed layer and the conductive oxide layer each comprise the same metal. The metal should be conductive in its metallic state and should remain conductive when partially or fully oxidized. Generally, the perovskite-seed layer has a perovskite or perovskite-like crystal structure and lattice parameters which are similar to the perovskite dielectric layer formed thereon. At a given deposition temperature, the crystal quality and other properties of the perovskite dielectric will generally be enhanced by depositing it on a surface having a similar crystal structure. Undesirable crystal structure formation will generally be minimized and lower processing temperatures may be used to deposit the perovskite dielectric layer.
    Type: Grant
    Filed: February 21, 1996
    Date of Patent: May 6, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Howard R. Beratan