Abstract: A high electron mobility transistor includes a channel layer, a barrier layer on the channel layer, source and drain contacts on the barrier layer, a gate contact between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer that comprises a charge dissipation material directly contacts the upper surface of the barrier layer and a second passivation layer comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. In some embodiments, at least one recess may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses.

Abstract: A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.

Abstract: A high electron mobility transistor (HEMT) includes a substrate comprising a first surface and a second surface on opposing sides of the substrate, a channel layer on the first surface of the substrate opposite the substrate, a barrier layer on the channel layer, a source contact comprising a first ohmic contact on an upper surface of the barrier layer, and a via extending from the second surface of the substrate to the first ohmic contact.

Abstract: A packaged electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.

Abstract: A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1 DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.

Abstract: A high electron mobility transistor (HEMT) includes a substrate comprising a first surface and a second surface on opposing sides of the substrate, a channel layer on the first surface of the substrate opposite the substrate, a barrier layer on the channel layer, a source contact comprising a first ohmic contact on an upper surface of the barrier layer, and a via extending from the second surface of the substrate to the first ohmic contact.

Abstract: A gallium nitride based monolithic microwave integrated circuit includes a substrate, a channel layer on the substrate and a barrier layer on the channel layer. A recess is provided in a top surface of the barrier layer. First gate, source and drain electrodes are provided on the barrier layer opposite the channel layer, with a bottom surface of the first gate electrode in direct contact with the barrier layer. Second gate, source and drain electrodes are also provided on the barrier layer opposite the channel layer. A gate insulating layer is provided in the recess in the barrier layer, and the second gate electrode is on the gate insulating layer opposite the barrier layer and extending into the recess. The first gate, source and drain electrodes comprise the electrodes of a depletion mode transistor, and the second gate, source and drain electrodes comprise the electrodes of an enhancement mode transistor.

Abstract: A packaged electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.

Abstract: A device includes a substrate; a buffer layer on the substrate; a barrier layer on the buffer layer, a source electrically coupled to the barrier layer; a gate electrically coupled to the barrier layer; and a drain electrically coupled to the barrier layer. The device further includes an electron concentration reduction structure arranged with at least one of the following: in the barrier layer and on the barrier layer. The electron concentration reduction structure is configured to at least one of the following: reduce electron concentration around the gate, reduce electron concentration around an edge of the gate, reduce electron concentration, increase power gain, increase efficiency, decouple the gate from the drain, decouple the gate from the source, and reduce capacitance.

Abstract: A high electron mobility transistor includes a channel layer, a barrier layer on the channel layer, source and drain contacts on the barrier layer, a gate contact between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer that comprises a charge dissipation material directly contacts the upper surface of the barrier layer and a second passivation layer comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. In some embodiments, at least one recess may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses.

Abstract: A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.

Abstract: A gallium nitride based monolithic microwave integrated circuit includes a substrate, a channel layer on the substrate and a barrier layer on the channel layer. A recess is provided in a top surface of the barrier layer. First gate, source and drain electrodes are provided on the barrier layer opposite the channel layer, with a bottom surface of the first gate electrode in direct contact with the barrier layer. Second gate, source and drain electrodes are also provided on the barrier layer opposite the channel layer. A gate insulating layer is provided in the recess in the barrier layer, and the second gate electrode is on the gate insulating layer opposite the barrier layer and extending into the recess. The first gate, source and drain electrodes comprise the electrodes of a depletion mode transistor, and the second gate, source and drain electrodes comprise the electrodes of an enhancement mode transistor.

Abstract: A gallium nitride based monolithic microwave integrated circuit includes a substrate, a channel layer on the substrate and a barrier layer on the channel layer. A recess is provided in a top surface of the barrier layer. First gate, source and drain electrodes are provided on the barrier layer opposite the channel layer, with a bottom surface of the first gate electrode in direct contact with the barrier layer. Second gate, source and drain electrodes are also provided on the barrier layer opposite the channel layer. A gate insulating layer is provided in the recess in the barrier layer, and the second gate electrode is on the gate insulating layer opposite the barrier layer and extending into the recess. The first gate, source and drain electrodes comprise the electrodes of a depletion mode transistor, and the second gate, source and drain electrodes comprise the electrodes of an enhancement mode transistor.

Abstract: A packaged electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.

Abstract: A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.

Abstract: A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.

Abstract: A transistor device including a field plate is described. One embodiment of such a device includes a field plate separated from a semiconductor layer by a thin spacer layer. In one embodiment, the thickness of spacer layer separating the field plate from the semiconductor layers is less than the thickness of spacer layer separating the field plate from the gate. In another embodiment, the non-zero distance separating the field plate from the semiconductor layers is about 1500 ? or less. Devices according to the present invention can show capacitances which are less drain bias dependent, resulting in improved linearity.

Abstract: A web page personalization system comprises a profile database and a profile manager. The profile database stores profiles for users. The profiles are comprised of segments of profile information for the users. The profile manager receives a request over an Internet for a group of segments of profile information about a user from a requestor. The request includes an anonymized identifier stored on a device for the user. The profile manager identifies a profile from the profiles for the user in the profile database using the anonymized identifier. The profile is comprised of the segments of the profile information about the user. The profile manager sends a portion of the profile information corresponding to the group of segments in an anonymized form in a reply over the Internet to the requestor. The requestor uses the group of segments to generate a personalized web page for the user.

Abstract: A method and apparatus for managing a personalization database. The computer system selects a number of segments of profile information about a user from a plurality of segments of the profile information about the user located in a human resources database. A record for the user in the personalization database is identified by the computer system, wherein an anonymized identifier for the user is used to locate the record. The number of segments selected is placed, by the computer system, into the record for the user in the personalization database, wherein a profile manager for the personalization database handles requests for information about users.

Abstract: Data traffic, such as wireless data traffic egressing to the Internet, is aggregated at one or more regional aggregation hubs, and a portion(s) of data traffic associated with a subscriber(s) of interest is captured at the regional aggregation hub(s). Data traffic associated with subscribers can be aggregated at an access concentrator(s) and respective public Internet Protocol (IP) addresses can be given to respective subscribers. The data traffic can be aggregated at the regional aggregation hub(s) and data traffic associated with a subscriber(s) of interest can be identified based at least in part on the public IP address(es) of the respective subscriber(s) of interest. The data traffic associated with a subscriber(s) of interest can be captured and provided to a consumer (e.g., law enforcement, service provider) who desires such data.