Abstract: A method and system to estimate lead time for delivery of a good is disclosed. In aspects, the method performs steps of: receiving a user request to transport the good; identifying a plurality of drivers for transporting the good within a virtual area; determining an expected response time to receive an acceptance of a job corresponding to the user request from a driver in the plurality of drivers; estimating an expected lead time using the expected response time and an expected travel time; and transmitting the expected lead time to the user.

Abstract: An adjustable antenna positioning system feed is disclosed herein. The adjustable antenna positioning system feed includes a feed base, a splash plate assembly, and a feed insert. The feed base is configured to be coupled to a reflector. The splash plate assembly is configured to be removably coupled to the feed base. The adjustable antenna positioning system feed is in a primary arrangement when directly coupled. The feed insert is positioned between the feed base and the splash plate. The adjustable antenna positioning system feed is in a secondary arrangement when the feed insert is coupled with the feed base and the splash plate.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

Abstract: Methods and systems for processing requests with load-dependent throttling. The system compares a count of active job requests being currently processed for a user associated with a new job request with an active job cap number for that user. When the count of active job requests being currently processed for that user does not exceed the active job cap number specific to that user, the job request is added to an active job queue for processing. However, when the count of active job requests being currently processed for that user exceeds the active job cap number, the job request is placed on a throttled queue to await later processing when an updated count of active job requests being currently processed for that user is below the active job cap number. Once the count is below the cap, the throttle request is moved to the active job queue for processing.

Abstract: A multitenancy system that includes a host provider, a programmable device, and multiple tenants is provided. The host provider may publish a multitenancy mode sharing and allocation policy that includes a list of terms to which the programmable device and tenants can adhere. The programmable device may include a secure device manager configured to operate in a multitenancy mode to load a tenant persona into a given partial reconfiguration (PR) sandbox region on the programmable device. The secure device manager may be used to enforce spatial isolation between different PR sandbox regions and temporal isolation between successive tenants in one PR sandbox region.

Abstract: Methods and systems for processing requests with load-dependent throttling. The system compares a count of active job requests being currently processed for a user associated with a new job request with an active job cap number for that user. When the count of active job requests being currently processed for that user does not exceed the active job cap number specific to that user, the job request is added to an active job queue for processing. However, when the count of active job requests being currently processed for that user exceeds the active job cap number, the job request is placed on a throttled queue to await later processing when an updated count of active job requests being currently processed for that user is below the active job cap number. Once the count is below the cap, the throttle request is moved to the active job queue for processing.

Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

Abstract: An apparatus to facilitate enabling secure state-clean during configuration of partial reconfiguration bitstreams on accelerator devices is disclosed. The apparatus includes a security engine to perform, as part of a PR configuration sequence for a new partial reconfiguration (PR) persona corresponding to a PR bitstream, a first clear operation to clear previously-set persona configuration bits in the region; perform, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and perform, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation.

Abstract: Methods and systems for processing requests with load-dependent throttling. The system compares a count of active job requests being currently processed for a user associated with a new job request with an active job cap number for that user. When the count of active job requests being currently processed for that user does not exceed the active job cap number specific to that user, the job request is added to an active job queue for processing. However, when the count of active job requests being currently processed for that user exceeds the active job cap number, the job request is placed on a throttled queue to await later processing when an updated count of active job requests being currently processed for that user is below the active job cap number. Once the count is below the cap, the throttle request is moved to the active job queue for processing.

Abstract: An apparatus to facilitate enabling secure state-clean during configuration of partial reconfiguration bitstreams on accelerator devices is disclosed. The apparatus includes a security engine to receive an incoming partial reconfiguration (PR) bitstream corresponding to a new PR persona to configure a region of the apparatus; perform, as part of a PR configuration sequence for the new PR persona, a first clear operation to clear previously-set persona configuration bits in the region; perform, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and perform, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation, the second clear operation performed using a persona-dependent mask corresponding to the new PR persona.

Abstract: An integrated circuit includes a buffer circuit, a memory circuit, and a controller circuit that determines if the memory circuit stores information that is valid and determines whether to transmit the information stored in the memory circuit to the buffer circuit based on credits that indicate an amount of storage space available in the buffer circuit. The controller circuit transmits the information to the buffer circuit if the credits indicate that sufficient storage space is available in the buffer circuit to store the information.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

Abstract: An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, multiplexers, and a validator. In one implementation, the validator is to: receive design rule information for the multiplexers, the design rule information referencing the contention set, wherein the contention set identifies a determined harmful bitstream configuration for each multiplexer instance of the multiplexers, and wherein the contention set comprises a mapping of contents of a user bitstream to configuration bits of the multiplexers; receive, at the validator of the apparatus, the user bitstream for programming the multiplexers of the apparatus; analyze, at the validator using the design rule information, the user bitstream against the contention set at a programming time of the apparatus; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

Abstract: An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

Abstract: Modified macrophage immune cells are provided for treatment of cancer and other diseases. In particular said macrophages express chimeric antigen receptors (CAR). The single chain variable fragment (scFv) may be directed against thymidine kinase 1 (TK1) or hypoxanthine guanine phosphoribosyltransferase (HPRT). The signaling domain may be derived from a Toll-like receptor (TLR).

Abstract: A three dimensional circuit system includes first and second integrated circuit (IC) dies. The first IC die includes programmable logic circuits arranged in sectors and first programmable interconnection circuits having first router circuits. The second IC die includes non-programmable circuits arranged in regions and second programmable interconnection circuits having second router circuits. Each of the regions in the second IC die is vertically aligned with at least one of the sectors in the first IC die. Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection. The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits. The circuit system may include additional IC dies. The first and second IC dies and any additional IC dies are coupled in a vertically stacked configuration.

Abstract: A system may include a host processor, a coprocessor for accelerating tasks received from the host processor, and one or more memory dies mounted to the coprocessor. The coprocessor and the memory die may be part of an integrated circuit package. The memory die may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor over through-silicon vias. Each logic sector may include one or more data registers that are loaded with configuration data from the memory die. Multiple data registers may be loaded with configuration data simultaneously. The configuration data may be loaded onto an array of configuration memory cells using the data registers. Multiple data registers may be pipelined to allow simultaneous loading of configuration data into multiple sub-arrays of the array of configuration memory cells.

Abstract: Methods and apparatus for extracting a setting of configuration bits to create an exclusion configuration for providing protection against peek and poke attacks in a multi-tenant usage model of a configurable device is provided. The device may host multiple parties that do not trust each other. Peek and poke attacks are orchestrated by tapping (peeking) and driving (poking) wires associated with other parties. Such attacks may be disabled by excluding the settings of configuration bits that would allow these attacks by other parties. This set of configuration bits that should be excluded for preventing all peek and poke attacks creates the exclusion configuration. Methods are described that disable a particular class of peek and/or poke attacks through the use of partial reconfiguration. Methods and apparatus are described to dynamically detect peek and/or poke attacks.