Patents by Inventor Scott Weber

Scott Weber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11379645
    Abstract: Methods and apparatus for extracting a setting of configuration bits to create an exclusion configuration for providing protection against peek and poke attacks in a multi-tenant usage model of a configurable device is provided. The device may host multiple parties that do not trust each other. Peek and poke attacks are orchestrated by tapping (peeking) and driving (poking) wires associated with other parties. Such attacks may be disabled by excluding the settings of configuration bits that would allow these attacks by other parties. This set of configuration bits that should be excluded for preventing all peek and poke attacks creates the exclusion configuration. Methods are described that disable a particular class of peek and/or poke attacks through the use of partial reconfiguration. Methods and apparatus are described to dynamically detect peek and/or poke attacks.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Scott Weber, Sean R. Atsatt, David Goldman
  • Patent number: 11352439
    Abstract: Modified macrophage immune cells are provided for treatment of cancer and other diseases.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: June 7, 2022
    Inventors: Kim Leslie O'Neill, Scott Weber
  • Publication number: 20220166124
    Abstract: An adjustable antenna positioning system feed is disclosed herein. The adjustable antenna positioning system feed includes a feed base, a splash plate assembly, and a feed insert. The feed base is configured to be coupled to a reflector. The splash plate assembly is configured to be removably coupled to the feed base. The adjustable antenna positioning system feed is in a primary arrangement when directly coupled. The feed insert is positioned between the feed base and the splash plate. The adjustable antenna positioning system feed is in a secondary arrangement when the feed insert is coupled with the feed base and the splash plate.
    Type: Application
    Filed: November 24, 2021
    Publication date: May 26, 2022
    Inventors: Keith Ayotte, Sandeep Palreddy, Scott Weber, Tyler McSorley, Nicholas Keith
  • Publication number: 20210330770
    Abstract: Modified T-cells have paratopes against human TK1 epitopes, are made by producing monoclonal antibodies that are specific to TK1, creating chimeric antigen receptors (CARs) by fusion of the single-chain variable fragments (scFv) of the monoclonal antibodies to T-cell signalling domains, and transducing the CARs to the T-cells.
    Type: Application
    Filed: July 2, 2021
    Publication date: October 28, 2021
    Inventors: Kim Leslie O'Neill, Scott Weber
  • Publication number: 20210311537
    Abstract: A circuit system includes a power control circuit that generates multiple voltage identifiers. Multiple voltage regulator circuits generate multiple supply voltages based on the voltage identifiers. The supply voltages are provided to multiple integrated circuit dies. The power control circuit varies the voltage identifiers based on changes in metrics associated with the integrated circuit dies to cause the voltage regulator circuits to vary the supply voltages. Integrated circuit dies receive supply voltages from voltage regulator circuits through power delivery networks. The integrated circuit dies provide voltage sense signals that indicates the supply voltages. The voltage regulator circuits adjust the supply voltages based on the voltage sense signals to compensate for voltage drops in the power delivery networks.
    Type: Application
    Filed: June 18, 2021
    Publication date: October 7, 2021
    Applicant: Intel Corporation
    Inventors: Archanna Srinivasan, Ravi Gutala, Scott Weber, Aravind Dasu, Mahesh Iyer, Eriko Nurvitadhi
  • Publication number: 20210313988
    Abstract: A three dimensional circuit system includes first and second integrated circuit (IC) dies. The first IC die includes programmable logic circuits arranged in sectors and first programmable interconnection circuits having first router circuits. The second IC die includes non-programmable circuits arranged in regions and second programmable interconnection circuits having second router circuits. Each of the regions in the second IC die is vertically aligned with at least one of the sectors in the first IC die. Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection. The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits. The circuit system may include additional IC dies. The first and second IC dies and any additional IC dies are coupled in a vertically stacked configuration.
    Type: Application
    Filed: June 22, 2021
    Publication date: October 7, 2021
    Applicant: Intel Corporation
    Inventors: Scott Weber, Aravind Dasu, Ravi Gutala, Mahesh Iyer, Eriko Nurvitadhi, Archanna Srinivasan, Sean Atsatt, James Ball
  • Publication number: 20210311517
    Abstract: A circuit system includes a first voltage regulator circuit that generates a first supply voltage for an integrated circuit die based on a first control signal. The first voltage regulator circuit generates a first feedback signal based on the first supply voltage. The circuit system also includes a second voltage regulator circuit that generates a second supply voltage for an integrated circuit die based on a second control signal. The second voltage regulator circuit generates a second feedback signal based on the second supply voltage. The circuit system also includes a third voltage regulator circuit that generates the first control signal based on the first feedback signal and the second control signal based on the second feedback signal. The circuit system may include fully integrated, on-board, and on-package voltage regulator circuits.
    Type: Application
    Filed: June 18, 2021
    Publication date: October 7, 2021
    Applicant: Intel Corporation
    Inventors: Archanna Srinivasan, Ravi Gutala, Scott Weber, Aravind Dasu, Mahesh Iyer, Eriko Nurvitadhi
  • Publication number: 20210313991
    Abstract: A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 7, 2021
    Applicant: Intel Corporation
    Inventors: Archanna Srinivasan, Ravi Gutala, Scott Weber, Aravind Dasu, Mahesh Iyer, Eriko Nurvitadhi
  • Patent number: 11052138
    Abstract: A nucleic acid encoding a chimeric antigen receptor (CAR) comprising a single-chain variable fragment (scFv) operatively linked to a signaling domain that polarizes a macrophage to an M1 macrophage; wherein the nucleic acid is operatively linked to a macrophage specific promoter; and wherein the scFv is specific for a human antigen. Monocytes or macrophages comprising such a nucleic acid.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: July 6, 2021
    Assignee: Thunder Biotech Inc.
    Inventors: Kim Leslie O'Neill, Scott Weber
  • Publication number: 20210117268
    Abstract: An apparatus to facilitate runtime fault detection, fault location, and circuit recovery in an accelerator device is disclosed. In one implementation, the accelerator device comprises a sensor network comprising a plurality of sensors; a secure device manager (SDM); and a sensor aggregator communicably coupled to the sensor network and the SDM. In one implementation, the sensor aggregator can receive sensor data from the sensor network; analyze the sensor data to detect a fault condition; determine a spatial location of the fault condition based on the sensor data; and generate an event for the SDM to cause the SDM to mitigate the fault condition.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 22, 2021
    Applicant: Intel Corporation
    Inventors: Patrick Koeberl, Scott Weber, Alpa Trivedi, Steffen Schulz, Sriram Vangal
  • Publication number: 20210110069
    Abstract: An apparatus to facilitate enabling secure state-clean during configuration of partial reconfiguration bitstreams on accelerator devices is disclosed. The apparatus includes a security engine to receive an incoming partial reconfiguration (PR) bitstream corresponding to a new PR persona to configure a region of the apparatus; perform, as part of a PR configuration sequence for the new PR persona, a first clear operation to clear previously-set persona configuration bits in the region; perform, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and perform, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation, the second clear operation performed using a persona-dependent mask corresponding to the new PR persona.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Applicant: Intel Corporation
    Inventors: Alpa Trivedi, Scott Weber, Steffen Schulz, Patrick Koeberl
  • Publication number: 20210110099
    Abstract: An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 15, 2021
    Applicant: Intel Corporation
    Inventors: Furkan Turan, Patrick Koeberl, Alpa Trivedi, Steffen Schulz, Scott Weber
  • Patent number: 10828355
    Abstract: Modified T-cells have paratopes against human TK1 epitopes, are made by producing monoclonal antibodies that are specific to TK1, creating chimeric antigen receptors (CARs) by fusion of the single-chain variable fragments (scFv) of the monoclonal antibodies to T-cell signalling domains, and transducing the CARs to the T-cells.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: November 10, 2020
    Inventors: Kim Leslie O'Neill, Scott Weber
  • Patent number: 10824500
    Abstract: A VIN verification system allow an accurate detection of incorrectly entered VIN in an electronic file followed by correction of the incorrectly entered VIN. A server of the VIN verification system verify characters and letters of the VIN in the electronic file to detect data entry and/or transmission errors. The server upon determining that the characters and entered in the VIN are incorrect will then replace the characters and letters with alternate or substitute characters and letters and generate a new VIN in the electronic file. The server will reexamine the new VIN to validate the new VIN, and then transmit the electronic file to another web application for further processing.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: November 3, 2020
    Assignee: UNITED SERVICES AUTOMOBILE ASSOCIATION (USAA)
    Inventors: Michael Shoemaker, Scott Weber
  • Patent number: 10821162
    Abstract: Modified T-cells have paratopes against human TK1 epitopes, are made by producing monoclonal antibodies that are specific to TK1, creating chimeric antigen receptors (CARs) by fusion of the single-chain variable fragments (scFv) of the monoclonal antibodies to T-cell signalling domains, and transducing the CARs to the T-cells.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: November 3, 2020
    Inventors: Kim Leslie O'Neill, Scott Weber
  • Publication number: 20200228388
    Abstract: A multitenancy system that includes a host provider, a programmable device, and multiple tenants is provided. The host provider may publish a multitenancy mode sharing and allocation policy that includes a list of terms to which the programmable device and tenants can adhere. The programmable device may include a secure device manager configured to operate in a multitenancy mode to load a tenant persona into a given partial reconfiguration (PR) sandbox region on the programmable device. The secure device manager may be used to enforce spatial isolation between different PR sandbox regions and temporal isolation between successive tenants in one PR sandbox region.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Steffen Schulz, Patrick Koeberl, Alpa Narendra Trivedi, Scott Weber
  • Publication number: 20200211969
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Publication number: 20200055279
    Abstract: A multi-layer film or laminate is disclosed in which an olefinic polymer layer is adhered to a metal foil layer without the use of an adhesive. The olefinic polymer layer contains an olefinic polymer in combination with a transition metal salt. The addition of the transition metal salt greatly improves the peel strength of the laminate.
    Type: Application
    Filed: August 20, 2019
    Publication date: February 20, 2020
    Inventors: Jeffrey Haley, Robert Scott Weber
  • Patent number: 10434153
    Abstract: Modified T-cells have paratopes against human TK1 epitopes, are made by producing monoclonal antibodies that are specific to TK1, creating chimeric antigen receptors (CARs) by fusion of the single-chain variable fragments (scFv) of the monoclonal antibodies to T-cell signalling domains, and transducing the CARs to the T-cells.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: October 8, 2019
    Inventors: Kim Leslie O'Neill, Scott Weber
  • Patent number: 10394990
    Abstract: Devices and methods for initializing one or more registers of a programmable integrated circuit (IC) to store an initial condition value are provided. A first bitstream that programs the region of the IC to supply the initial condition value to the one or more registers is first programmed on the IC. Then, once the registers are initialized with the initial condition value, a second bitstream is subsequently programmed to the region of the IC to supply values associated with a function of the design to the one or more registers.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: August 27, 2019
    Assignee: Altera Corporation
    Inventors: Kalen Brunham, Kevin Nealis, Yi Peng, Scott Weber