Patents by Inventor Scott Weber

Scott Weber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10821162
    Abstract: Modified T-cells have paratopes against human TK1 epitopes, are made by producing monoclonal antibodies that are specific to TK1, creating chimeric antigen receptors (CARs) by fusion of the single-chain variable fragments (scFv) of the monoclonal antibodies to T-cell signalling domains, and transducing the CARs to the T-cells.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: November 3, 2020
    Inventors: Kim Leslie O'Neill, Scott Weber
  • Publication number: 20200228388
    Abstract: A multitenancy system that includes a host provider, a programmable device, and multiple tenants is provided. The host provider may publish a multitenancy mode sharing and allocation policy that includes a list of terms to which the programmable device and tenants can adhere. The programmable device may include a secure device manager configured to operate in a multitenancy mode to load a tenant persona into a given partial reconfiguration (PR) sandbox region on the programmable device. The secure device manager may be used to enforce spatial isolation between different PR sandbox regions and temporal isolation between successive tenants in one PR sandbox region.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Steffen Schulz, Patrick Koeberl, Alpa Narendra Trivedi, Scott Weber
  • Publication number: 20200211969
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Publication number: 20200055279
    Abstract: A multi-layer film or laminate is disclosed in which an olefinic polymer layer is adhered to a metal foil layer without the use of an adhesive. The olefinic polymer layer contains an olefinic polymer in combination with a transition metal salt. The addition of the transition metal salt greatly improves the peel strength of the laminate.
    Type: Application
    Filed: August 20, 2019
    Publication date: February 20, 2020
    Inventors: Jeffrey Haley, Robert Scott Weber
  • Patent number: 10434153
    Abstract: Modified T-cells have paratopes against human TK1 epitopes, are made by producing monoclonal antibodies that are specific to TK1, creating chimeric antigen receptors (CARs) by fusion of the single-chain variable fragments (scFv) of the monoclonal antibodies to T-cell signalling domains, and transducing the CARs to the T-cells.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: October 8, 2019
    Inventors: Kim Leslie O'Neill, Scott Weber
  • Patent number: 10394990
    Abstract: Devices and methods for initializing one or more registers of a programmable integrated circuit (IC) to store an initial condition value are provided. A first bitstream that programs the region of the IC to supply the initial condition value to the one or more registers is first programmed on the IC. Then, once the registers are initialized with the initial condition value, a second bitstream is subsequently programmed to the region of the IC to supply values associated with a function of the design to the one or more registers.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: August 27, 2019
    Assignee: Altera Corporation
    Inventors: Kalen Brunham, Kevin Nealis, Yi Peng, Scott Weber
  • Publication number: 20190095567
    Abstract: Methods and apparatus for extracting a setting of configuration bits to create an exclusion configuration for providing protection against peek and poke attacks in a multi-tenant usage model of a configurable device is provided. The device may host multiple parties that do not trust each other. Peek and poke attacks are orchestrated by tapping (peeking) and driving (poking) wires associated with other parties. Such attacks may be disabled by excluding the settings of configuration bits that would allow these attacks by other parties. This set of configuration bits that should be excluded for preventing all peek and poke attacks creates the exclusion configuration. Methods are described that disable a particular class of peek and/or poke attacks through the use of partial reconfiguration. Methods and apparatus are described to dynamically detect peek and/or poke attacks.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Applicant: Intel Corporation
    Inventors: Scott Weber, Sean R. Atsatt, David Goldman
  • Publication number: 20190091309
    Abstract: Modified T-cells have paratopes against human TK1 epitopes, are made by producing monoclonal antibodies that are specific to TK1, creating chimeric antigen receptors (CARs) by fusion of the single-chain variable fragments (scFv) of the monoclonal antibodies to T-cell signalling domains, and transducing the CARs to the T-cells.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 28, 2019
    Inventors: Kim Leslie O'Neill, Scott Weber
  • Publication number: 20190095113
    Abstract: A system for maintaining reconfigurable partitions in an integrated device includes a first buffer having channels that store configuration data and a mask. The system also includes first decompression circuitry having a second buffer coupled to the first buffer that stores the configuration data and second decompression circuitry having a third buffer coupled to the first buffer that stores the mask. The system also includes partition maintenance circuitry that applies the mask to the configuration data after the first decompression circuitry has decompressed the configuration data and the second decompression circuitry has decompressed the mask.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: Sean R. Atsatt, Andrew Draper, Ting Lu, Steve Tuyen Vu, Scott Weber
  • Publication number: 20190070277
    Abstract: Modified T-cells have paratopes against human TK1 epitopes, are made by producing monoclonal antibodies that are specific to TK1, creating chimeric antigen receptors (CARs) by fusion of the single-chain variable fragments (scFv) of the monoclonal antibodies to T-cell signalling domains, and transducing the CARs to the T-cells.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 7, 2019
    Inventors: Kim Leslie O'Neill, Scott Weber
  • Publication number: 20190070276
    Abstract: Modified T-cells have paratopes against human TK1 epitopes, are made by producing monoclonal antibodies that are specific to TK1, creating chimeric antigen receptors (CARs) by fusion of the single-chain variable fragments (scFv) of the monoclonal antibodies to T-cell signalling domains, and transducing the CARs to the T-cells.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 7, 2019
    Inventors: Kim Leslie O'Neill, Scott Weber
  • Patent number: 10223014
    Abstract: A system for maintaining reconfigurable partitions in an integrated device includes a first buffer having channels that store configuration data and a mask. The system also includes first decompression circuitry having a second buffer coupled to the first buffer that stores the configuration data and second decompression circuitry having a third buffer coupled to the first buffer that stores the mask. The system also includes partition maintenance circuitry that applies the mask to the configuration data after the first decompression circuitry has decompressed the configuration data and the second decompression circuitry has decompressed the mask.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Sean R. Atsatt, Andrew Draper, Ting Lu, Steve Tuyen Vu, Scott Weber
  • Publication number: 20180143777
    Abstract: A system may include a host processor, a coprocessor for accelerating tasks received from the host processor, and one or more memory dies mounted to the coprocessor. The coprocessor and the memory die may be part of an integrated circuit package. The memory die may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor over through-silicon vias. Each logic sector may include one or more data registers that are loaded with configuration data from the memory die. Multiple data registers may be loaded with configuration data simultaneously. The configuration data may be loaded onto an array of configuration memory cells using the data registers. Multiple data registers may be pipelined to allow simultaneous loading of configuration data into multiple sub-arrays of the array of configuration memory cells.
    Type: Application
    Filed: November 22, 2016
    Publication date: May 24, 2018
    Inventors: Aravind Dasu, Scott Weber, Jun Pin Tan, Arifur Rahman
  • Publication number: 20180143860
    Abstract: A host processor may utilize a coprocessor to accelerate the performance of a task. Upon receiving a acceleration request from the host processor, the coprocessor may identify and select an available logic sector within the coprocessor that can be used to perform a task associated with the acceleration request. In some cases, the selected logic sector may not be configured to perform the task, in which case the selected logic sector may be reconfigured. The configuration bit stream used to reconfigure the selected logic sector to perform the task may be retrieved from a stacked memory die mounted on the coprocessor, or, if the configuration bit stream is not stored in the stacked memory die, the configuration bit stream may be retrieved from an external memory through the host processor. Load balancing may be performed to dynamically allocate additional logic sectors to time-critical tasks.
    Type: Application
    Filed: November 22, 2016
    Publication date: May 24, 2018
    Inventors: Aravind Dasu, Scott Weber, Jun Pin Tan, Arifur Rahman
  • Patent number: 9941867
    Abstract: One embodiment relates to a pulse latch that includes a latch control logic circuit and a pulse latch circuit. The latch control logic circuit generates a plurality of control signals and selects a control signal of the plurality of control signals to output to the pulse latch circuit. Each control signal of the plurality of control signals causes the pulse latch circuit to operate in a different operating mode. Another embodiment relates to a method of generating control signaling for a pulse latch. A clock signal and a shifted clock signal are received. A plurality of inputs to a multiplexor are generated using the clock signal and the shifted clock signal. An input of the plurality of inputs is selected as an output of the multiplexor. The input is selected by the multiplexor using a plurality of multiplexor configuration bits.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: April 10, 2018
    Assignee: Altera Corporation
    Inventor: Scott Weber
  • Publication number: 20170249603
    Abstract: The present disclosure involves systems, software, and computer-implemented methods for allowing independent adjustment for different areas of a payment instrument image. An example method includes updating an image property of an area of a clearing payment instrument image associated with a tangible payment instrument including a payee, a payor, an amount, and an authorization, the tangible payment instrument to be submitted for electronic transaction clearing, wherein the clearing payment instrument image is associated with a first value of the image property, the image property of the area is updated to a second value different than the first value of the image property, and the area of the clearing payment instrument image includes less than the entire clearing payment image; and storing the updated clearing payment instrument image in response to updating the image property.
    Type: Application
    Filed: July 18, 2016
    Publication date: August 31, 2017
    Inventors: Scott Weber, Rian Maloney
  • Publication number: 20170200059
    Abstract: The present disclosure involves systems, software, and computer-implemented methods for applying correction macros to a clearing payment instrument image. An example method includes identifying a correction macro including one or more image processing actions to apply to a first clearing payment instrument image; associating the correction macro with a first attribute of the first clearing payment instrument image; and determining that the correction macro is to be applied to a second clearing payment instrument including a second attribute based on the second attribute matching the first attribute associated with the correction macro.
    Type: Application
    Filed: January 11, 2016
    Publication date: July 13, 2017
    Applicant: Digital Check Corporation
    Inventors: Rian Maloney, Scott Weber
  • Publication number: 20170166657
    Abstract: Modified macrophage immune cells are provided for treatment of cancer and other diseases.
    Type: Application
    Filed: November 22, 2016
    Publication date: June 15, 2017
    Inventors: Kim Leslie O'Neill, Scott Weber
  • Publication number: 20170098201
    Abstract: The present disclosure involves systems, software, and computer-implemented methods for allowing independent adjustment for different areas of a payment instrument image. An example method includes updating an image property of an area of a clearing payment instrument image associated with a tangible payment instrument including a payee, a payor, an amount, and an authorization, the tangible payment instrument to be submitted for electronic transaction clearing, wherein the clearing payment instrument image is associated with a first value of the image property, the image property of the area is updated to a second value different than the first value of the image property, and the area of the clearing payment instrument image includes less than the entire clearing payment image; and storing the updated clearing payment instrument image in response to updating the image property.
    Type: Application
    Filed: July 18, 2016
    Publication date: April 6, 2017
    Inventors: Scott Weber, Rian Maloney
  • Patent number: D778805
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: February 14, 2017
    Assignees: Amatrimara Inc., Bentech Inc.
    Inventors: Michael Klinck, Scott Strong, Scott Weber, Robert Benninghoff