Abstract: A method for manufacturing a recess gate in a semiconductor device includes forming a device isolation structure on a substrate to define an active region, forming a hard mask pattern over the substrate to selectively expose at least a portion of the active region, forming a recess pattern in the active region through an etching process using the hard mask pattern as an etch barrier, removing the hard mask pattern, forming a gate insulating layer over the substrate, and forming a gate electrode over the gate insulating layer to cover at least the recess pattern.

Abstract: A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.

Abstract: A method for fabricating a transistor including a bulb-type recess channel includes forming a bulb-type recess pattern in a substrate, forming a gate insulating layer over the substrate and the bulb-type recess pattern, forming a first gate conductive layer over the gate insulating layer, forming a void movement blocking layer over the first gate conductive layer in the bulb-type recess pattern, and forming a second gate conductive layer over the void movement blocking layer and the first gate conductive layer.

Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

Abstract: A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.

Abstract: Disclosed is a method for manufacturing a transistor in a semiconductor device, which can improve a device's refresh characteristics. The method includes: providing a silicon substrate having active and field regions; performing a channel ion implantation into the substrate; sequentially forming a hard mask film and a photoresist pattern exposing a gate formation region where the channel ion implantation occurred; performing a second, higher concentration channel ion implantation using the photoresist pattern as a mask, forming doped regions in the substrate at the gate formation region and sides; etching a hard mask using the photoresist pattern as a barrier; removing the photoresist pattern; etching the substrate using a portion of the remaining hard mask as a barrier forming a groove; removing the remaining hard mask; forming a gate in the groove where the hard mask was removed; and forming source and drain regions at both sides of the gate.

Abstract: The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.

Abstract: The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.

Abstract: Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.

Abstract: A gate structure of a semiconductor memory device capable of preventing a poly void generation by forming a hard mask and maintaining a hysteresis area within a certain value. The gate structure of the semiconductor memory device includes: a gate insulation layer formed on a semiconductor substrate; a gate electrode formed on the gate insulation layer, wherein the gate electrode is formed by stacking a polysilicon layer and a metal layer; and a hard mask formed on the gate electrode, wherein a hysteresis area between the hard mask and the gate electrode materials is a equal to or less than approximately 2×1012 ° C.-dyne/cm2.

Abstract: The present invention provides a method for fabricating a semiconductor device having a dual gate dielectric structure capable of obtaining a simplified process and improving device reliability. The method includes the steps of: forming an insulation layer on a substrate; forming a nitride layer on the insulation layer; selectively etching the nitride layer in a predetermined region of the substrate; performing a radical oxidation process to form an oxide layer on the insulation layer and the etched nitride layer; forming a gate conductive layer on the oxide layer; and performing a selective etching process to the gate conductive layer, the oxide layer, the nitride layer and the insulation layer, so that the first dielectric structure formed in the predetermined region includes the insulation layer and the oxide layer and the second gate dielectric structure formed in regions other than the predetermined region includes the insulation layer, the nitride layer and the oxide layer.

Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

Abstract: Disclosed is a method for fabricating a semiconductor device with a polymetal gate electrode formed by a partial gate recessing process. The method includes the steps of forming a gate structure including a gate dielectric layer, a polysilicon layer, a metal layer, an etch stop layer and a sacrificial layer sequentially formed on a substrate; selectively performing a re-oxidation process to the gate structure; forming a spacer on each sidewall of the gate structure; implanting ions in the substrate for forming source/drain regions; selectively removing the sacrificial layer of the gate structure to form a recess; and filling an insulating hard mask into the recess for use in a self-aligned contact etching process.

Abstract: The present invention relates to a method for fabricating a recessed gate structure. The method includes the steps of: selectively etching a substrate to form a plurality of openings; forming a gate oxide layer on the openings and the substrate; forming a first conductive silicon layer on the gate oxide layer to form a plurality of valleys at a height equal to or greater than a thickness remaining after an intended pattern is formed; planarizing the first conductive silicon layer until the thickness remaining after the intended pattern formation is obtained, so that the valleys are removed; forming a second conductive layer on a planarized first conductive silicon layer; and selectively etching the second conductive layer, the first conductive silicon layer and the gate oxide layer to form a plurality of the recessed gate structures.

Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

Abstract: Disclosed is a method for manufacturing a semiconductor device, more particularly to a method of forming a spacer on side-walls of a titanium polycide gate. The method for manufacturing the semiconductor device is as follows. There is provided a semiconductor substrate in which a gate oxide layer, a polysilicon layer, a titanium silicide layer and a patterned hard mask layer are sequentially formed. Herein, the titanium polycide gate is fabricated by an etching step employing the patterned hard mask. Afterward, the substrate is thermal-treated at temperature of 700˜750° C. according to a gate re-oxidation process, thereby forming a re-oxidation layer on side-walls of the gate and on the substrate surface. Next, an oxide layer for spacer is deposited on the resultant at process temperature of 350˜750 C., and a nitride layer is deposited on the oxide layer.

Abstract: The present invention is related to a method for fabricating a transistor with a polymetal gate electrode structure. The method includes the steps of: forming a gate insulation layer on a substrate; forming a patterned gate stack structure on the gate insulation layer, wherein the patterned stack structure includes a polysilicon layer as a bottom layer and a metal layer as an upper layer; forming a silicon oxide-based capping layer along a profile containing the patterned gate stack structure and on the gate insulation layer at a predetermined temperature that prevents oxidation of the metal layer; and performing a gate re-oxidation process.

Abstract: The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.

Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

Abstract: The present invention provides a method for fabricating a semiconductor device having a dual gate dielectric structure capable of obtaining a simplified process and improving device reliability. The method includes the steps of: forming an insulation layer on a substrate; forming a nitride layer on the insulation layer; selectively etching the nitride layer in a predetermined region of the substrate; performing a radical oxidation process to form an oxide layer on the insulation layer and the etched nitride layer; forming a gate conductive layer on the oxide layer; and performing a selective etching process to the gate conductive layer, the oxide layer, the nitride layer and the insulation layer, so that the first dielectric structure formed in the predetermined region includes the insulation layer and the oxide layer and the second gate dielectric structure formed in regions other than the predetermined region includes the insulation layer, the nitride layer and the oxide layer.