Abstract: The MOSFET fabrication method allows application of a self-aligned contact (SAC) process while maintaining a metal gate, such as a tungsten gate, to have a uniform thickness. The process involves forming a metal oxide film during the formation of a metal gate structure of the MOSFET device. The metal oxide film is formed by subjecting the gate structure through a rapid thermal oxidation (RTO) treatment and then to an N2O plasma treatment. The treatments allow the thickness of the metal oxide to be precisely controlled. The metal oxide acts as an insulator, which prevents electrical shorts between the gate structure and a contact plug even if a misalignment of occurs during the SAC process. This is an improvement from the conventional practice of separately forming a SAC barrier film after the formation of the metal gate structure and thus saves money, time, and increases reliability and productivity. Also the performance characteristics of the device is enhanced.

Abstract: A method for forming an element isolation film of a semiconductor device and the semiconductor device. A pad insulator is constructed on a semiconductor substrate. An over-etching process is performed to recess the semiconductor substrate to a predetermined depth while giving a pad insulator pattern. After an insulator spacer is formed at the side wall of the pad insulator pattern, the exposed region of the semiconductor substrate is thermally oxidized to grow an oxide which is, then, removed to form a recess. An element isolation film is formed in the recess by break-through field oxidation and high temperature field oxidation. The element isolation film thus obtained can prevent the field oxide “ungrowth” phenomenon and at the same time mitigate the field oxide thinning effect as well as improve the properties of the gate oxide.

Abstract: The present invention relates to a method for forming a gate electrode in a semiconductor device that is more tolerant of misalignment during contact formation processing. The improved gate structure reduces the formation of shorts between the gate electrode and subsequently formed conductors such as DRAM bit lines and storage lines. The gate electrode is formed from a damascene metal gate electrode having adjacent insulating spacers by partially etching the metal gate electrode to form a trench; depositing a nitride film; and etching the nitride film to form additional protective insulators above outer portions of the gate electrodes. With these protective insulators in place, subsequent contact processing becomes more tolerant of misalignment, reducing rework and improving yield.

Abstract: A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a NMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.

Abstract: A method for fabricating a dual metal gate structure for a semiconductor device uses a damascene process to form a second gate in addition to a single gate process for forming a first gate. After a semiconductor substrate having a PMOS region and an NMOS region formed therein is provided, a first gate insulating layer and a first metal layer are formed on the substrate and patterned. Thus, the first gate is formed in a first region, either the PMOS region or the NMOS region, and a dummy gate is formed in a second region. Next, a spacer is formed on each sidewall of the first gate and the dummy gate, and a source/drain region is formed in the substrate adjacent each side of the first gate and the dummy gate. Then, a dielectric layer is formed on the resultant structure and polished to expose the first metal layer, and the dummy gate is removed to expose a portion of the substrate in the second region.

Abstract: A method of forming a gate in a semiconductor device includes forming a dummy gate insulating layer on a semiconductor substrate having a field oxide layer isolating the device, depositing a dummy gate polysilicon layer and a hard mask layer on the dummy gate insulating layer sequentially, patterning the hard mask layer into a mask pattern and patterning the dummy gate polysilicon layer using the mask pattern as an etch barrier, forming spacers at both sidewalls of the dummy gate polysilicon layer, depositing an insulating interlayer on the resultant structure after forming the spacers, exposing a surface of the dummy gate polysilicon layer by carrying out an oxide layer CMP process having a high selection ratio against the dummy gate polysilicon layer, forming a damascene structure by removing the dummy gate polysilicon layer and the dummy gate insulating layer using the insulating interlayer as another etch barrier, depositing a gate insulating layer and a gate metal layer on the entire surface of the semic

Abstract: The present invention relates to a method of forming a damascene gate electrode of highly integrated MOS transistor capable of easily removing a dummy polysilicon layer. The disclosed comprises the steps of forming a dummy gate insulating layer and a polysilicon layer for a dummy gate on a wafer; forming an interlayer insulating layer on the wafer; polishing the interlayer insulating layer to expose a top surface of the dummy polysilicon layer; and wet etching the exposed dummy polysilicon layer using a spin etching process.

Abstract: A method of forming a semiconductor device gate including the steps of forming a dummy gate insulating layer on a semiconductor substrate having an isolating field oxide layer, successively depositing a dummy gate silicon layer and a hard mask layer on the dummy gate insulating layer, forming a hard mask layer and patterning the dummy gate silicon layer using the mask pattern as an etch barrier, forming a thermal oxide layer at both sidewalls of the dummy gate silicon layer by thermal oxidation on the resultant structure, forming spacers at both sidewalls of the dummy gate silicon layer, depositing an insulating interlayer on the resultant structure, polishing the insulating interlayer to expose the dummy gate silicon layer, forming a damascene structure by removing the dummy gate silicon and insulating layers, depositing a gate insulating layer and a gate metal layer on an entire surface of the semiconductor substrate having the damascene structure, and polishing the gate metal and insulating layers, thereby

Abstract: A method of forming dual-metal gates in a semiconductor device, including the steps of providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas respectively, forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates, polishing the insulating interlayer until the dummy gates are exposed, forming a first groove defining a first metal gate area by selectively removing one of the dummy gates formed in the PMOS and NMOS areas, forming a first gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including the first groove successively, forming a first metal gate in the first groove by etching the first metal layer and first gate insulating layer until the insulating interlayer is exposed, forming a second groove defining a second metal gate area by removing the remaining dummy gate, forming a second gate insulating layer and a second metal layer on the entire area o

Abstract: The present invention provides a method for fabricating an improved gate electrode of a MOSFET device. And the method for fabricating a MOSFET device having a polycide gate to which a titanium silicide is applied comprises the steps of sequentially forming a polysilicon layer on a gate insulating layer and a titanium layer in this order, forming a capping layer on the titanium layer and forming a titanium silicide layer by performing a rapid thermal process in nitrogen atmosphere.

Abstract: A method of fabricating a semiconductor device using a damascene metal gate including the steps of forming a damascene gate oxide layer and a damascene gate electrode on a semiconductor substrate, forming a trench at an upper part of the damascene gate electrode by selectively etching a portion of the damascene gate electrode to a predetermined thickness, forming an insulating layer in the trench on the damascene gate electrode, forming an insulating interlayer on an upper surface of the entire structure, and forming a contact hole exposing a portion of the semiconductor substrate by selectively etching the insulating interlayer.

Abstract: The present invention relates to a method for forming a gate electrode in a semiconductor device that is more tolerant of misalignment during contact formation processing. The improved gate structure reduces the formation of shorts between the gate electrode and subsequently formed conductors such as DRAM bit lines and storage lines. The gate electrode is formed from a damascene metal gate electrode having adjacent insulating spacers by partially etching the metal gate electrode to form a trench; depositing a nitride film; and etching the nitride film to form additional protective insulators above outer portions of the gate electrodes. With these protective insulators in place, subsequent contact processing becomes more tolerant of misalignment, reducing rework and improving yield.

Abstract: The present invention provides a method for fabricating an improved gate electrode of a MOSFET device. And the method for fabricating a MOSFET device having a polycide gate to which a titanium silicide is applied comprises the steps of sequentially forming a polysilicon layer on a gate insulating layer and a titanium layer in this order, forming a capping layer on the titanium layer and forming a titanium silicide layer by performing a rapid thermal process in nitrogen atmosphere.

Abstract: The MOSFET fabrication method allows application of a self-aligned contact (SAC) process while maintaining a metal gate, such as a tungsten gate, to have a uniform thickness. The process involves forming a metal oxide film during the formation of a metal gate structure of the MOSFET device. The metal oxide film is formed by subjecting the gate structure through a rapid thermal oxidation (RTO) treatment and then to an N2O plasma treatment. The treatments allow the thickness of the metal oxide to be precisely controlled. The metal oxide acts as an insulator, which prevents electrical shorts between the gate structure and a contact plug even if a misalignment of occurs during the SAC process. This is an improvement from the conventional practice of separately forming a SAC barrier film after the formation of the metal gate structure and thus saves money, time, and increases reliability and productivity. Also the performance characteristics of the device is enhanced.

Abstract: It is an object of the present invention to provide a method for forming a semiconductor MOSFET device having polycide gate electrode by preventing the sidewall screen oxide from being abnormally formed, and according to an aspect of the present invention, there is provided a method for fabricating a MOSFET comprising a polycide gate electrode with titanium silicide on a semiconductor substrate, comprising the steps of: forming a polysilicon layer and a titanium layer on a gate insulating layer; performing a rapid thermal process for forming a titanium silicide layer under nitrogen-filled environment; and removing a titanium nitride layer, which is a byproduct formed on the titanium silicide layer during said b) step of performing the rapid thermal process.

Abstract: A method of forming a gate electrode in a semiconductor device which can effectively prevent abnormal oxidation of a metal layer without occurring thermal budget and the deterioration of a gate insulating layer during gate re-oxidation process, is disclosed. In the present invention, one selected from a group consisting of an iridium(Ir) layer, a ruthenium(Ru) layer and an osmium(Os) layer capable of forming a nonvolatile conductive metal oxide layer, is used as a metal layer of a gate electrode instead of a W layer in conventional art. Therefore, although a gate re-oxidation process is performed by a well known method, it is effectively prevented that the metal layer is abnormally oxidized, thereby forming an uniform oxide layer on the side wall of the gate. Furthermore, since the oxide layer is conductive, the resistivity of the gate electrode is reduced.

Abstract: A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. A thin SiO2 layer is thermally grown on top of the semiconductor device by using a wet H2/O2 or a dry O2. And then, an aluminum oxide layer is formed on top of the semiconductor substrate with doping a dopant in situ. A conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer and the Al2O3 layer are patterned into the gate structure. The dopant is a material selected from a group consisting of Si, Zr, Hf, Nb or the like.

Abstract: A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. An aluminum oxide (Al2O3) layer is deposited on top of the semiconductor substrate and then, silicon ions plasma doping is carried out. Thereafter, the Al2O3 layer doped with silicon ions is annealed in the presence of oxygen gas or nitrous oxygen to remove a metallic vacancy in the Al2O3 layer. Subsequently, a conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer is patterned into the gate structure.

Abstract: A method for forming a titanium polycide gate, comprising the steps of: forming a gate oxide and a doped polysilicon layer over the semiconductor substrate, in turn; implanting impurity ions into the doped polysilicon layer to form an amorphous phase silicon layer in the surface of the polysilicon layer; forming an amorphous phase titanium silicide layer over the amorphous phase silicon layer; carrying out heat-treatment to transform the amorphous phase titanium silicide layer into a crystalline phase titanium silicide layer and to transform the amorphous phase silicon layer into the crystalline silicon layer; and patterning the crystalline phase titanium silicide layer, the polysilicon layer including the crystalline phase silicon layer and the gate oxide to form the titanium polycide gate.

Abstract: A method for forming an element isolation film of a semiconductor device and the semiconductor device. A pad insulator is constructed on a semiconductor substrate. An over-etching process is performed to recess the semiconductor substrate to a predetermined depth while giving a pad insulator pattern. After an insulator spacer is formed at the side wall of the pad insulator pattern, the exposed region of the semiconductor substrate is thermally oxidized to grow an oxide which is, then, removed to form a recess. An element isolation film is formed in the recess by break-through field oxidation and high temperature field oxidation. The element isolation film thus obtained can prevent the field oxide “ungrowth” phenomenon and at the same time mitigate the field oxide thinning effect as well as improve the properties of the gate oxide.