Abstract: The present disclosure relates to a technical idea for minimizing a signal correction process between users using brain activity-based clustering technology. More specifically, the present disclosure relates to technology for minimizing a signal correction process between users by clustering a brain signal of a measurement subject into a specific clustering model and determining an intention of the measurement subject using an intention determination model learned on the specific clustering model.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a substrate having a substantially horizontal upper surface; first to Nth layers disposed in horizontal layers on the substrate and spaced apart from each other above the substrate in a vertical direction, wherein each of the first to Nth layers comprises a plurality of conductive lines; an insulating layer disposed to fill spaces between the conductive lines; a hole having sidewalls that extends in the vertical direction through the insulating layer and between the conductive lines to expose, in sidewalls of the hole, conductive lines of the first to Nth layers; a variable resistance layer disposed on sidewalls of the hole; and a conductive pillar disposed to fill the hole in which the variable resistance layer is formed, wherein N is a natural number of two or more.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a cell electrode structure disposed on the substrate and including interlayer insulating layers and gate electrode layers that are alternately stacked, a trench penetrating the cell structure on the substrate, a charge storage structure disposed on a sidewall surface of the trench, and a channel structure disposed adjacent to the charge storage structure and extending in a direction parallel to the sidewall surface. The channel structure includes a separate hole conduction layer and an adjacent and separate electron conduction layer. A control channel layer disposed on a control dielectric layer is a portion of the electron conduction layer configured to electrically connect to the channel structure, and to the charge storage structure. A control dielectric layer and a charge barrier layer are discrete but contiguous from the control channel structure to the charge storage structure.

Abstract: Disclosed is an antenna module for minimizing the occurrence of breakdowns during the manufacturing thereof by adhering heterogeneous material, which adheres heterogeneous material base substrates with adhesive substrates. The disclosed antenna module has a plurality of first radiation patterns formed on the upper surface of a first base substrate, has a plurality of second radiation patterns and a plurality of chipsets formed on the upper surface and the lower surface of a second base substrate disposed below the first base substrate, has a first adhesive substrate interposed between the first base substrate and the second base substrate, wherein the first adhesive substrate has air gap holes formed therein so as to form air gaps between the plurality of first radiation patterns and the plurality of second radiation patterns.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed on the substrate, a gate electrode layers disposed on the resistance change layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed in the substrate and contact different portions of the resistance change layer. The resistance change layer includes movable oxygen vacancies or movable metal ions.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, and a gate structure disposed on the substrate and including a hole pattern. The gate structure includes at least one gate electrode layer and at least one interlayer insulation layer which are alternately stacked, and the gate electrode layer protrudes toward a center of the hole pattern relative to the interlayer insulation layer. The nonvolatile memory device includes a first functional layer disposed along a sidewall surface of the gate structure inside the hole pattern, a second functional layer disposed on the first functional layer inside the hole pattern, and a channel layer extending in a direction perpendicular to the substrate inside the hole pattern and disposed to contact a cell portion of the second functional layer. The cell portion of the second functional layer indirectly covers a sidewall surface of the gate electrode layer.

Abstract: A nonvolatile memory device includes a substrate, a source electrode structure disposed on the substrate, a channel structure disposed to be contact a sidewall surface of the source electrode structure, a resistance change memory layer disposed on a sidewall surface of the channel structure, a drain electrode structure disposed to contact the resistance change memory layer, a plurality of gate dielectric structures extending in the first direction and disposed to be spaced apart from each other in a second direction, and a plurality of gate electrode structures disposed to extend in the first direction in the plurality of the gate dielectric structure.

Abstract: A nonvolatile memory device includes a substrate having an upper surface and a channel structure disposed over the substrate. The channel structure includes at least one channel layer pattern and at least one interlayer insulation layer pattern, which are alternately stacked in a first direction perpendicular to the upper surface, and the channel structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a resistance change layer disposed over the substrate and on at least a portion of one sidewall surface of the channel structure, a gate insulation layer disposed over the substrate and on the resistance change layer, and a plurality of gate line structures disposed over the substrate, each contacting a first surface of the gate insulation layer and disposed to be spaced apart from each other in the second direction.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed over the substrate, a gate insulation layer disposed on the resistance change layer, a gate electrode layer disposed on the gate insulation layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed respectively over the substrate and disposed to contact a different portion of the resistance change layer.

Abstract: In a method, a stack structure including a plurality of first interlayer sacrificial layers and a plurality of second interlayer sacrificial layers that are alternately stacked is formed over a substrate. A trench penetrating the stack structure is formed. A channel layer covering a sidewall surface of the trench is formed. The plurality of first interlayer sacrificial layers are selectively removed to form a plurality of first recesses. The plurality of first recesses are filled with a conductive material to form a plurality of channel contact electrode layers. The plurality of second interlayer sacrificial layers are selectively removed to form a plurality of second recesses. A plurality of interfacial insulation layers, a plurality of ferroelectric layers and a plurality of gate electrode layers are formed in the plurality of second recesses.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a source electrode structure disposed on the substrate, and a channel structure disposed over the substrate and disposed to contact one sidewall surface of the source electrode structure. In addition, the nonvolatile memory device includes a drain electrode structure disposed to contact one sidewall surface of the channel structure over the substrate. In addition, the nonvolatile memory device includes a plurality of ferroelectric structures extending in a first direction perpendicular to the substrate in the channel structure and disposed to be spaced apart from each other along the second direction perpendicular to the first direction. In addition, the nonvolatile memory device includes a gate electrode structure disposed in each of the plurality of ferroelectric structure to extend along the first direction.

Abstract: The present invention relates to a polyarylene sulfide having more improved miscibility with other polymer materials or fillers, and a method of preparing the same. At least part of end groups of the main chain of the polyarylene sulfide is carboxyl group (—COON) or amine group (—NH2).

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a gate electrode structure disposed on the substrate, a gate dielectric layer covering at least a portion of a sidewall surface of the gate electrode structure on the substrate, a channel layer and a resistance change structure that are sequentially disposed on the gate dielectric layer, and a plurality of bit line structures disposed inside the resistance change structure.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a source electrode structure disposed on the substrate, a channel structure disposed to be contact a sidewall surface of the source electrode structure, a resistance change memory layer disposed on a sidewall surface of the channel structure, a drain electrode structure disposed to contact the resistance change memory layer, a plurality of gate dielectric structures extending in the first direction and disposed to be spaced apart from each other in a second direction, and a plurality of gate electrode structures disposed to extend in the first direction in the plurality of the gate dielectric structure.

Abstract: A vertical memory device according to an aspect includes a substrate, a first gate electrode structure disposed on the substrate and a second gate electrode structure spaced apart from the first gate electrode structure in a first direction substantially perpendicular to the substrate, a channel contact electrode layer disposed between the first gate electrode structure and the second gate electrode structure, and a channel layer extending along the first direction and in contact with the channel contact electrode layers and the first and the second gate electrode structures.

Abstract: A display apparatus includes a display panel, a display panel driver and a first connection wire. The display panel includes a substrate and a display layer disposed on a first surface of the substrate. The display panel driver applies a driving signal to the display panel. The display panel driver is disposed on a second surface opposite to the first surface of the substrate. The first connection wire is disposed at a first side surface connecting the first and second surfaces of the substrate. The first connection wire connects electrically the display panel with the display panel driver.

Abstract: A nonvolatile memory device according to an aspect of the present disclosure includes a substrate having a channel layer, a gate dielectric layer structure disposed on the channel layer, a ferroelectric layer disposed on the gate dielectric layer structure, and a gate electrode layer disposed on the ferroelectric layer. The gate dielectric layer structure has a positive capacitance. The ferroelectric layer has a negative capacitance. The gate dielectric layer structure includes a charge tunneling layer, a charge trap layer and a charge barrier layer disposed on the channel layer.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a substrate having a substantially horizontal upper surface; first to Nth layers disposed in horizontal layers on the substrate and spaced apart from each other above the substrate in a vertical direction, wherein each of the first to Nth layers comprises a plurality of conductive lines; an insulating layer disposed to fill spaces between the conductive lines; a hole having sidewalls that extends in the vertical direction through the insulating layer and between the conductive lines to expose, in sidewalls of the hole, conductive lines of the first to Nth layers; a variable resistance layer disposed on sidewalls of the hole; and a conductive pillar disposed to fill the hole in which the variable resistance layer is formed, wherein N is a natural number of two or more.

Abstract: The present invention relates to a polyarylene sulfide which has more improved compatibility with other polymer materials or fillers, and a method for preparing the same. The polyarylene sulfide is characterized in that at least part of end groups of the main chain of the polyarylene sulfide is hydroxyl group (—OH), the polyarylene sulfide contains iodine bonded to its main chain and free iodine, and the content of iodine bonded to the main chain and free iodine is 10 to 10,000 ppmw.