Abstract: A manufacturing method of a liquid crystal display includes: forming an etch target layer including a conductive material on a first substrate; forming a first mask layer on the etch target layer; forming a block copolymer coating layer including a plurality of polymers on the first mask layer; processing the block copolymer coating layer to form a block copolymer pattern layer including first and second polymer blocks; removing one of the first or second polymer blocks to form a second mask pattern layer; etching the first mask layer by using the second mask pattern layer as an etching mask to form a first mask pattern layer; and etching the etch target layer by using the first mask pattern layer as an etching mask to form a first electrode. The first electrode includes a plurality of the first minute patterns extending in a predetermined direction and having a polarization function.

Abstract: A display substrate includes a base substrate; a first metal pattern disposed on the base substrate and comprising a first signal line and a first electrode electrically connected to the first signal line; and a buffer pattern disposed at a corner between a sidewall surface of the first metal pattern and the base substrate.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract: An array substrate includes; a substrate, a gate line and a data line disposed on the substrate, a thin film transistor (“TFT”) electrically connected to the gate line and the data line, a light blocking member disposed on the substrate and a first color filter and a second color filter disposed on the substrate. The light blocking member covers a portion of the first color filter and the second color filter covers a portion of the light blocking member.

Abstract: A method of manufacturing a color filter substrate includes forming a plurality of trenches having a predetermined depth by etching a surface of a transparent substrate, disposing a color filter material in the plurality of trenches to form a color filter layer, and forming a transparent electrode on the transparent substrate including the color filter layer therein.

Abstract: A switching element includes an active pattern including a channel portion, a source portion connected to the channel portion, and a drain portion connected to the channel portion, the source portion, a gate electrode overlapping the channel portion of the active pattern, a gate insulation layer disposed between the channel portion of the active pattern and the gate electrode, a source electrode disposed on the source portion of the active pattern to make ohmic contact with the source portion, and a drain electrode disposed on the drain portion of the active pattern to make ohmic contact with the drain portion. The drain portion and the channel portion of the active pattern include the same or substantially the same material.

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.

Abstract: A method of manufacturing a color filter substrate includes forming a plurality of trenches having a predetermined depth by etching a surface of a transparent substrate, disposing a color filter material in the plurality of trenches to form a color filter layer, and forming a transparent electrode on the transparent substrate including the color filter layer therein.

Abstract: An array substrate includes; a substrate, a gate line and a data line disposed on the substrate, a thin film transistor (“TFT”) electrically connected to the gate line and the data line, a light blocking member disposed on the substrate and a first color filter and a second color filter disposed on the substrate. The light blocking member covers a portion of the first color filter and the second color filter covers a portion of the light blocking member.

Abstract: A thin film transistor substrate includes a base substrate, an active pattern, a gate insulation pattern and a gate electrode. The active pattern is disposed on the base substrate. The active pattern includes a source electrode, a drain electrode, and a channel disposed between the source electrode and the drain electrode. The gate insulation pattern and the gate electrode overlap with the channel. The gate insulation pattern is disposed between the channel and the gate electrode. The source electrode and the drain electrode each include a fluorine deposition layer.

Abstract: A thin film transistor array panel including a substrate; a channel region disposed on the substrate and including oxide semiconductor disposed on the substrate; a source electrode and a drain electrode connected to the oxide semiconductor and facing each other at both sides, centered on the oxide semiconductor; an insulating layer disposed on the oxide semiconductor; and a gate electrode disposed on the insulating layer. The drain electrode includes a first drain region and a second drain region; the charge mobility of the first drain region is greater than that of the second drain region, the source electrode includes a first source region and a second source region, and the charge mobility of the first source region is greater than that of the second source region.

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract: A switching element includes an active pattern including a channel portion, a source portion connected to the channel portion, and a drain portion connected to the channel portion, the source portion, a gate electrode overlapping the channel portion of the active pattern, a gate insulation layer disposed between the channel portion of the active pattern and the gate electrode, a source electrode disposed on the source portion of the active pattern to make ohmic contact with the source portion, and a drain electrode disposed on the drain portion of the active pattern to make ohmic contact with the drain portion. The drain portion and the channel portion of the active pattern include the same or substantially the same material.

Abstract: A display substrate includes a base substrate, a data line disposed on the base substrate, a gate line crossing the data line, a first insulation layer disposed on the base substrate, an active pattern disposed on the first insulation layer and comprising a channel comprising an oxide semiconductor, a source electrode connected to the channel, and a drain electrode connected to the channel, a second insulation layer disposed on the active pattern, and contacting to the source electrode and the drain electrode, a gate electrode disposed on the second insulation layer, and overlapping with the channel, a passivation layer disposed on the gate electrode and the second insulation layer, and a pixel electrode electrically connected to the drain electrode through a first contact hole formed through the passivation layer and the second insulation layer.

Abstract: A thin film transistor display panel according to an exemplary embodiment of the present invention includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed on the first insulating layer, a second insulating layer formed on the semiconductor layer, and a gate electrode formed on the second insulating layer, in which the first insulating layer includes a light blocking material, and a thickness of the first insulating layer is greater than or equal to a thickness of the second insulating layer.

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract: A method for forming a minute pattern mask includes forming an etching target layer on a substrate. A convex pattern including a plurality of convex parts is formed on the etching target layer. A resin composition is coated on the convex pattern to form a resin layer including a first region neighboring the convex part and a second region positioned between the neighboring convex parts. The resin layer is ashed or etched to form the plurality of first resin patterns. The plurality of first resin patterns is processed to form a minute pattern mask including a plurality of second resin patterns. The etching target layer is etched using the plurality of second resin patterns as an etch mask to form a minute pattern.

Abstract: A thin film transistor substrate including a base substrate; an active pattern disposed on the base substrate and including a source electrode, a drain electrode, and a channel including an oxide semiconductor disposed between the source electrode and the drain electrode; a gate insulation pattern disposed on the active pattern; a gate electrode disposed on the gate insulation pattern and overlapping with the channel; and a light-blocking pattern disposed between the base substrate and the active pattern.