Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract: A thin film transistor substrate includes a base substrate, an active pattern, a gate insulation pattern and a gate electrode. The active pattern is disposed on the base substrate. The active pattern includes a source electrode, a drain electrode, and a channel disposed between the source electrode and the drain electrode. The gate insulation pattern and the gate electrode overlap with the channel. The gate insulation pattern is disposed between the channel and the gate electrode. The source electrode and the drain electrode each include a fluorine deposition layer.

Abstract: Provided is a thin film transistor and thin film transistor panel array. The thin film transistor includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and partially overlapping with the gate electrode; a source electrode and a drain electrode spaced apart from each other with respect to a channel region of the semiconductor layer; an insulating layer disposed between the gate electrode and the semiconductor layer; and a barrier layer disposed between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode, in which the barrier layer comprises graphene. An ohmic contact is provided based on the type of material used for the semiconductor layer.

Abstract: A thin film transistor substrate includes a base substrate, an active pattern disposed on the base substrate, a gate insulation pattern disposed on the active pattern, a gate electrode disposed on the gate insulation pattern and overlapping the channel, and a light-blocking pattern disposed between the base substrate and the active pattern and having a size greater than the active pattern. The active pattern includes a source electrode, a drain electrode, and a channel disposed between the source electrode and the drain electrode.

Abstract: A thin film transistor array panel is provided that includes: a gate electrode that is disposed on an insulating substrate; a gate insulating layer that is disposed on the gate electrode; an oxide semiconductor that is disposed on the gate insulating layer; a blocking layer that is disposed on the oxide semiconductor; a source electrode and a drain electrode that are disposed on the blocking layer; a passivation layer that is disposed on the source electrode and drain electrode; and a pixel electrode that is disposed on the passivation layer. The blocking layer includes a first portion that is covered by the source electrode and drain electrode and a second portion that is not covered by the source electrode and drain electrode, and the first portion and the second portion include different materials.

Abstract: A liquid crystal display is provided. The liquid crystal display includes a substrate. A thin film transistor is disposed on the substrate. A passivation layer is disposed on the thin film transistor. A pixel electrode is disposed on the passivation layer. A minute space layer is disposed on the pixel electrode and includes a liquid crystal injection hole. A first overcoat is disposed on the minute space layer. A common electrode is disposed on the first overcoat. A capping layer covers the liquid crystal injection hole. The capping layer includes graphene.

Abstract: A liquid crystal display according to an exemplary embodiment of the present invention includes: a pixel electrode including a first subpixel electrode and a second subpixel electrode with a gap therebetween; a common electrode facing the pixel electrode; and a liquid crystal layer formed between the pixel electrode and the common electrode, and including a plurality of liquid crystal molecules, wherein the first and second subpixel electrodes include a plurality of minute branches, the first and second subpixel electrodes include a plurality of subregions having different length directions of the minute branches, and the width of the minute branches is wider than an interval between the neighboring minute branches.

Abstract: A method is provided for forming a fine pattern. In the method, a first fine pattern and a first metal pattern are formed by respectively patterning a first fine pattern layer on a base substrate and a first metal layer on the first fine pattern layer. A second fine pattern layer and a second metal layer are sequentially formed over the first fine pattern and the first metal pattern. The second metal layer is patterned, so that a second metal pattern between adjacent portions of the first fine pattern. The second fine pattern layer is patterned using the second metal pattern as a mask, so that a second fine pattern is formed between adjacent portions of the first fine pattern.

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract: In a method of manufacturing a glass plate for a display device, a protection film is formed on a mother glass plate. The protection film is patterned to form a protection film pattern which prevents ion exchange. Chemically strengthening the mother glass plate includes exchanging alkaline ions of the mother glass plate including the protection film pattern are exchanged with metal ions of a molten salt to form a first chemically strengthened portion, a non-strengthened portion and a second chemically strengthened portion. The upper surface of the protection film pattern is cut in the scribe line area to separate the glass plate at the non-strengthened portion of the mother glass plate, from the mother glass plate.

Abstract: A liquid crystal display capable of reducing the stray capacitance of a non-display region and a method of manufacturing the same. The liquid crystal display includes a first substrate, gate lines and data lines intersecting each other on the first substrate to define pixels, a second substrate arranged opposite to the first substrate, a common electrode formed in a display area of the second substrate in which an image is displayed, and a floating electrode formed in a non-display region of the second substrate in which no image is displayed.

Abstract: A display substrate includes a base substrate, a switching element, a gate line, a data line and a pixel electrode. Each of the gate line and the data line includes a first metal layer, and a second metal layer directly on the first metal layer. The switching element is on the base substrate, and includes a control electrode and an input electrode or an output electrode. The control electrode includes the first metal layer and excludes the second metal layer, and extends from the gate line. The input electrode or the output electrode includes a second metal layer and excludes the first metal layer. The input electrode extends from the data line. The pixel electrode is electrically connected to the output electrode of the switching element through a first contact hole, and includes a transparent conductive layer.

Abstract: A method for forming a minute pattern mask includes forming an etching target layer on a substrate. A convex pattern including a plurality of convex parts is formed on the etching target layer. A resin composition is coated on the convex pattern to form a resin layer including a first region neighboring the convex part and a second region positioned between the neighboring convex parts. The resin layer is ashed or etched to form the plurality of first resin patterns. The plurality of first resin patterns is processed to form a minute pattern mask including a plurality of second resin patterns. The etching target layer is etched using the plurality of second resin patterns as an etch mask to form a minute pattern.

Abstract: A thin film transistor array panel including a display area having a gate line, a data line insulated from and intersecting the gate line, a thin film transistor connected to the gate line and the data line, and a pixel electrode connected to the thin film transistor, and a peripheral area formed on the circumference of the display area, according to an exemplary embodiment of the present invention, includes: a driving signal line formed with the same layer as the gate line in the peripheral area and receiving an external signal; a connection signal line formed with the same layer as the data line in the peripheral area; a disconnection prevention member overlapping the side surface of the connection signal line on the connection signal line; and a connection assistance member formed on the disconnection prevention member and connecting the driving signal line and the connection signal line.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.

Abstract: A liquid crystal display is provided. The liquid crystal display includes a substrate. A thin film transistor is disposed on the substrate. A passivation layer is disposed on the thin film transistor. A pixel electrode is disposed on the passivation layer. A minute space layer is disposed on the pixel electrode and includes a liquid crystal injection hole. A first overcoat is disposed on the minute space layer. A common electrode is disposed on the first overcoat. A capping layer covers the liquid crystal injection hole. The capping layer includes graphene.

Abstract: A manufacturing method of a liquid crystal display includes: forming an etch target layer including a conductive material on a first substrate; forming a first mask layer on the etch target layer; forming a block copolymer coating layer including a plurality of polymers on the first mask layer; processing the block copolymer coating layer to form a block copolymer pattern layer including first and second polymer blocks; removing one of the first or second polymer blocks to form a second mask pattern layer; etching the first mask layer by using the second mask pattern layer as an etching mask to form a first mask pattern layer; and etching the etch target layer by using the first mask pattern layer as an etching mask to form a first electrode. The first electrode includes a plurality of the first minute patterns extending in a predetermined direction and having a polarization function.

Abstract: A display substrate includes a base substrate; a first metal pattern disposed on the base substrate and comprising a first signal line and a first electrode electrically connected to the first signal line; and a buffer pattern disposed at a corner between a sidewall surface of the first metal pattern and the base substrate.

Abstract: Provided is a thin film transistor array panel. The thin film transistor array panel according to exemplary embodiments of the present invention includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

Abstract: Provided is a thin film transistor and thin film transistor panel array. The thin film transistor includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and partially overlapping with the gate electrode; a source electrode and a drain electrode spaced apart from each other with respect to a channel region of the semiconductor layer; an insulating layer disposed between the gate electrode and the semiconductor layer; and a barrier layer disposed between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode, in which the barrier layer comprises graphene. An ohmic contact is provided based on the type of material used for the semiconductor layer.