Abstract: A semiconductor package may include a semiconductor chip and a substrate. The substrate may include a plurality of bonding pads for interfacing the semiconductor chip with a printed circuit board through conductive bumps that may be electrically connected to the bonding pads, respectively. The bonding pads may include non-solder mask defined (NSMD) bonding pads and solder mask defined (SMD) bonding pads that may be alternately arranged on the substrate. The SMD bonding pads may have sufficient reliability with respect to a drop test and the NSMD bonding pads may have sufficient reliability with respect to the board-level temperature cycle.

Abstract: A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.

Abstract: Semiconductor packages are provided to prevent a chip, such as a central processing unit (CPU) chip, from being degraded due to hot spot heat generated during the operation of the chip and absorbs thermomechanical stresses in interfaces between the chip, a thermal interface material (TIM) and a lid. The chip is electrically connected, e.g., flip-chip bonded, to a package substrate. The lid is thermally connected to and disposed over a back surface of the chip with the TIM interposed therebetween. A heat dissipation means adjacent the TIM is also located between the lid and the chip to prevent the hot spot effect.

Abstract: An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness of the chip attaching part is smaller than the thickness of the leads. The package device further includes bonding wires electrically connecting the chip to the leads, and a package body for encapsulating the semiconductor chip, bonding wires, die pad, and inner portions of the leads. A first thickness of the die pad is preferably between about 30-50% of a second thickness of the leads. An overall thickness of the package device is preferably equal to or less than 0.7 mm.

Abstract: An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness of the chip attaching part is smaller than the thickness of the leads. The package device further includes bonding wires electrically connecting the chip to the leads, and a package body for encapsulating the semiconductor chip, bonding wires, die pad, and inner portions of the leads. A first thickness of the die pad is preferably between about 30–50% of a second thickness of the leads. An overall thickness of the package device is preferably equal to or less than 0.7 mm.

Abstract: A printed circuit board and a semiconductor package module using the same in which solder joint reliability (SJR) is improved. The printed circuit board includes: a first terminal exposed to the external of the printed circuit board in a print circuit pattern to be connected to a solder ball of a semiconductor package; a second terminal exposed to the external of the printed circuit board in the printed circuit pattern to be connected to another printed circuit board; and a buffer layer, which is an insulating layer formed adjacent the first terminal, being formed of a thermal absorption material, e.g. an elastomer, configured to absorb thermal stress caused by any difference of coefficients of thermal expansion between the semiconductor package and the first terminal, wherein the printed circuit board is a multi-layered printed circuit board including alternately layered insulators and printed circuit patterns.

Abstract: A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.

Abstract: A solder bump structure includes a contact pad, an intermediate layer located over the contact pad, a solder bump located over the intermediate layer, and at least one metal projection extending upwardly from a surface of the intermediate layer and embedded within the solder bump. Any crack in the solder bump will tend to propagate horizontally through the bump material, and in this case, the metal projections act as obstacles to crack propagation. These obstacles have the effect of increasing the crack resistance, and further lengthen the propagation path of any crack as it travels through the solder bump material, thus decreasing the likelihood device failure.

Abstract: Semiconductor packages are provided to prevent a chip, such as a central processing unit (CPU) chip, from being degraded due to hot spot heat generated during the operation of the chip and absorbs thermomechanical stresses in interfaces between the chip, a thermal interface material (TIM) and a lid. The chip is electrically connected, e.g., flip-chip bonded, to a package substrate. The lid is thermally connected to and disposed over a back surface of the chip with the TIM interposed therebetween. A heat dissipation means adjacent the TIM is also located between the lid and the chip to prevent the hot spot effect.

Abstract: The present invention provides an LOC package wherein the lead frame is in direct contact with the semiconductor device. The lead frame, which includes openings, is positioned directly on the semiconductor device. An adhesive material is applied in the opening in the lead frame. This adhesive material contacts both the lead frame and the semiconductor device. The lead frame is therefore securely held to the semiconductor device. Wires can then be bonded to contact pads on the semiconductor device and to the lead frame.

Abstract: A solder bump structure includes a contact pad, an intermediate layer located over the contact pad, a solder bump located over the intermediate layer, and at least one metal projection extending upwardly from a surface of the intermediate layer and embedded within the solder bump. Any crack in the solder bump will tend to propagate horizontally through the bump material, and in this case, the metal projections act as obstacles to crack propagation. These obstacles have the effect of increasing the crack resistance, and further lengthen the propagation path of any crack as it travels through the solder bump material, thus decreasing the likelihood device failure.

Abstract: In one embodiment, a memory card comprises a card substrate, at least one memory chip attached to the card substrate, a control chip mounted on the memory chip, bonding wires electrically connecting the chips with the card substrate, a passive device attached to the card substrate near the memory chip, and a molded body encapsulating the memory chip, the control chip, the bonding wires and the passive device. In addition, the memory card comprises an adhesive spacer interposed between the same-sized chips to secure a wire loop of the bonding wires.

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other.

Abstract: A flip chip device may have a semiconductor chip with an active surface on which chip pads and a protective layer may be provided. Solder bumps may be provided on the active surface and electrically connected to the chip pads. And a solder bar may be provided on a portion of the protective layer. The solder bar may disperse thermal stress produced in the solder bumps. A metal core may be embedded within the solder bar. The flip chip device may be mounted on and flip-chip bonded to a substrate. The substrate may have land pads to which the solder bumps and the solder bar may be mechanically joined. The solder bar increases a joint area between the flip chip device and the substrate and reinforces solder connections therebetween.

Abstract: Provided is a method of fabricating an ultra thin flip-chip package. In the above method, an under barrier metal film is formed on a bond pad of a semiconductor chip. Three-dimensional structured solder bumps are formed on the under barrier metal film, each of the solder bumps including a bar portion and a ball portion disposed at an end of the bar portion. The semiconductor chip including the three-dimensional structured solder bumps is bonded to a solder layer on a printed circuit board to complete a flip-chip package. According to the present invention, by employing the three-dimensional structured solder bumps, it is possible to lower the height of the solder bumps, thereby improving the reliability of an ultra thin flip-chip package.

Abstract: Semiconductor packages are provided to prevent a chip, such as a central processing unit (CPU) chip, from being degraded due to hot spot heat generated during the operation of the chip and absorbs thermomechanical stresses in interfaces between the chip, a thermal interface material (TIM) and a lid. The chip is electrically connected, e.g., flip-chip bonded, to a package substrate. The lid is thermally connected to and disposed over a back surface of the chip with the TIM interposed therebetween. A heat dissipation means adjacent the TIM is also located between the lid and the chip to prevent the hot spot effect.

Abstract: A stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface. The lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip, and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.

Abstract: A semiconductor package comprises a board, a plurality of solder bump pads, a plurality of board pads, a plurality of distribution patterns, a plurality of contact pads, at least one chip, a plurality of bonding wire, an encapsulation part and a plurality of solder bumps. In order to reduce the height of the loop of the bonding wires for connecting the bonding pad on the semiconductor chip to the board pads on the board, the ends of the bonding wires are connected to the bonding pads and board pads respectively by wedge bonding. Thus, a very thin package can be obtained. In addition, a thin package stack can be obtained by stacking the very thin packages.

Abstract: A solder bump structure includes a contact pad, an intermediate layer located over the contact pad, a solder bump located over the intermediate layer, and at least one metal projection extending upwardly from a surface of the intermediate layer and embedded within the solder bump. Any crack in the solder bump will tend to propagate horizontally through the bump material, and in this case, the metal projections act as obstacles to crack propagation. These obstacles have the effect of increasing the crack resistance, and further lengthen the propagation path of any crack as it travels through the solder bump material, thus decreasing the likelihood device failure.

Abstract: A semiconductor package comprises a board, a plurality of solder bump pads, a plurality of board pads, a plurality of distribution patterns, a plurality of contact pads, at least one chip, a plurality of bonding wire, an encapsulation part and a plurality of solder bumps. In order to reduce the height of the loop of the bonding wires for connecting the bonding pad on the semiconductor chip to the board pads on the board, the ends of the bonding wires are connected to the bonding pads and board pads respectively by wedge bonding. Thus, a very thin package can be obtained. In addition, a thin package stack can be obtained by stacking the very thin packages.