Abstract: The present invention relates to an apparatus and method for encoding and decoding an image by skip encoding. The image-encoding method by skip encoding, which performs intra-prediction, comprises: performing a filtering operation on the signal which is reconstructed prior to an encoding object signal in an encoding object image; using the filtered reconstructed signal to generate a prediction signal for the encoding object signal; setting the generated prediction signal as a reconstruction signal for the encoding object signal; and not encoding the residual signal which can be generated on the basis of the difference between the encoding object signal and the prediction signal, thereby performing skip encoding on the encoding object signal.

Abstract: Provided are a device and a method for monitoring substrates to determine a processed state of the substrates and inspecting presence of abnormality in the processed substrates. A device for inspecting substrates includes a substrate mounting part moving relative to the substrate and for mounting a substrate, a measurement part for monitoring the substrate, a control part configured to control a movement path of the measurement part so that at least some regions are monitored from positions different from each other with respect to a plurality of substrates, and an analysis part configured to determine presence of abnormality from monitoring information about the plurality of substrates.

Abstract: Provided are a device and a method for monitoring substrates to determine a processed state of the substrates and inspecting presence of abnormality in the processed substrates. A device for inspecting substrates includes a substrate mounting part moving relative to the substrate and for mounting a substrate, a measurement part for monitoring the substrate, a control part configured to control a movement path of the measurement part so that at least some regions are monitored from positions different from each other with respect to a plurality of substrates, and an analysis part configured to determine presence of abnormality from monitoring information about the plurality of substrates.

Abstract: Provided are a device and a method for monitoring substrates to determine a processed state of the substrates and inspecting presence of abnormality in the processed substrates. A device for inspecting substrates includes a substrate mounting part moving relative to the substrate and for mounting a substrate, a measurement part for monitoring the substrate, a control part configured to control a movement path of the measurement part so that at least some regions are monitored from positions different from each other with respect to a plurality of substrates, and an analysis part configured to determine presence of abnormality from monitoring information about the plurality of substrates.

Abstract: Provided herein as a method of manufacturing a decorative flower, including forming a stem by cutting a leather sheet into two rectangular stem leather pieces and adhering the rear surfaces of the stem leather pieces to each other using an adhesive, folding a petal leather piece by cutting a leather sheet into the rectangular petal leather piece, applying the adhesive to first adhesive surfaces of the petal leather piece and folding the petal leather piece in half in the horizontal direction, making cuts in the petal leather piece in the vertical direction at designated intervals, applying the adhesive to a second adhesive surface of the petal leather piece and rolling the petal leather piece into a cylindrical shape about the stem, forming petals by spreading parts formed by the cuts, and decorating the lower portion of the stem leather piece with a running stitch after formation of the petals.

Abstract: A system-in-package, comprising a wafer level stack structure, including at least one first device chip including a first device region having a plurality of input/output(I/O) pads, and at least one second device chip including a second device region having a plurality of input/output(I/O) pads and a second peripheral region surrounding the second device region, wherein the size of the second device region is different from the size of the first device region, wherein the at least one first device chip and the at least one second device chip have approximately equal size; and a common circuit board to which the wafer level stack structure is connected.

Abstract: A system-in-package, comprising a wafer level stack structure, including at least one first device chip including a first device region having a plurality of input/output(I/O) pads, and at least one second device chip including a second device region having a plurality of input/output(I/O) pads and a second peripheral region surrounding the second device region, wherein the size of the second device region is different from the size of the first device region, wherein the at least one first device chip and the at least one second device chip have approximately equal size; and a common circuit board to which the wafer level stack structure is connected.

Abstract: Provided is a method of forming conductors (e.g., metal lines and/or bumps) for semiconductor devices and conductors formed from the same. First and second seed metal layers may be formed. At least one mask may be formed on a portion on which a conductor is to be formed. An exposed portion may be oxidized. The oxidized portion may be removed. A conductive structure may be formed on an upper surface of a portion which is not oxidized. The conductors may be metal lines and/or bumps. The conductive structures may be solder balls.

Abstract: A method of forming a wafer level stack structure, including forming a first wafer including a first device chip, wherein the first device chip includes a plurality of input/output (I/O) pads, forming a second wafer including a second device chip, wherein each second device chip contains a second plurality of I/O pads, the second device chip is approximately equal in size to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including a first device chip having a first plurality of input/output (I/O) pads and a second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected.

Abstract: A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.

Abstract: The present invention provides an LOC package wherein the lead frame is in direct contact with the semiconductor device. The lead frame, which includes openings, is positioned directly on the semiconductor device. An adhesive material is applied in the opening in the lead frame. This adhesive material contacts both the lead frame and the semiconductor device. The lead frame is therefore securely held to the semiconductor device. Wires can then be bonded to contact pads on the semiconductor device and to the lead frame.

Abstract: Provided is a method of forming conductors (e.g., metal lines and/or bumps) for semiconductor devices and conductors formed from the same. First and second seed metal layers may be formed. At least one mask may be formed on a portion on which a conductor is to be formed. An exposed portion may be oxidized. The oxidized portion may be removed. A conductive structure may be formed on an upper surface of a portion which is not oxidized. The conductors may be metal lines and/or bumps. The conductive structures may be solder balls.

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other.

Abstract: Provided is a method of fabricating an ultra thin flip-chip package. In the above method, an under barrier metal film is formed on a bond pad of a semiconductor chip. Three-dimensional structured solder bumps are formed on the under barrier metal film. each of the solder bumps including a bar portion and a ball portion disposed at an end of the bar portion. The semiconductor chip including the three-dimensional structured solder bumps is bonded to a solder layer on a printed circuit board to complete a flip-chip package. According to the present invention, by employing the three-dimensional structured solder bumps, it is possible to lower the height of the solder bumps, thereby improving the reliability of an ultra thin flip-chip package.

Abstract: An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness of the chip attaching part is smaller than the thickness of the leads. The package device further includes bonding wires electrically connecting the chip to the leads, and a package body for encapsulating the semiconductor chip, bonding wires, die pad, and inner portions of the leads. A first thickness of the die pad is preferably between about 30-50% of a second thickness of the leads. An overall thickness of the package device is preferably equal to or less than 0.7 mm.

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other.

Abstract: A semiconductor package with improved solder joint reliability, and a method of fabricating the same are provided. The semiconductor package comprises a printed circuit board (PCB) having a plurality of interconnection layers formed on its surface, and having a plurality of through holes connected to the interconnection layers. An adhesive member is attached to an upper surface of the PCB, and a semiconductor chip is electrically connected to the interconnection layers and mounted on an upper surface of the adhesive member. A solder connecting part fills each through hole so as to form a mechanically strong connection that is resistant to breakage during thermal transients and physical impacts.

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other.

Abstract: Provided is a method of fabricating an ultra thin flip-chip package. In the above method, an under barrier metal film is formed on a bond pad of a semiconductor chip. Three-dimensional structured solder bumps are formed on the under barrier metal film, each of the solder bumps including a bar portion and a ball portion disposed at an end of the bar portion. The semiconductor chip including the three-dimensional structured solder bumps is bonded to a solder layer on a printed circuit board to complete a flip-chip package. According to the present invention, by employing the three-dimensional structured solder bumps, it is possible to lower the height of the solder bumps, thereby improving the reliability of an ultra thin flip-chip package.