Patents by Inventor Sean D. Burns
Sean D. Burns has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10032632Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.Type: GrantFiled: October 4, 2016Date of Patent: July 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Christopher Arnold, Sean D. Burns, Yann Alain Marcel Mignot, Yongan Xu
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Publication number: 20180197738Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.Type: ApplicationFiled: October 17, 2017Publication date: July 12, 2018Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
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Patent number: 10002762Abstract: Multi-angled deposition and masking techniques are provided to enable custom trimming and selective removal of spacers that are used for patterning features at sub-lithographic dimensions. For example, a method includes forming a sacrificial mandrel on a substrate, and forming first and second spacers on opposing sidewalls of the sacrificial mandrel. The first and second spacers are formed with an initial thickness TS. A first angle deposition process is performed to deposit a material (e.g., insulating material or metallic material) at a first deposition angle A1 to form a first trim mask layer on an upper portion of the first spacer and the sacrificial mandrel while preventing the material from being deposited on the second spacer. A spacer etch process is performed to trim the first spacer to a first thickness T1, which is less than TS, using the first trim mask layer as an etch mask.Type: GrantFiled: September 9, 2016Date of Patent: June 19, 2018Assignee: International Business Machines CorporationInventors: Marc A. Bergendahl, Sean D. Burns, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
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Patent number: 9991156Abstract: An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a ? line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a ? line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an ? line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a ??? jog; a ??? jog; an ??? jog; a ??? jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.Type: GrantFiled: June 3, 2016Date of Patent: June 5, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
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Patent number: 9972533Abstract: A method for forming conductive contacts on a wafer comprises forming a first hardmask, planarizing layer, second hardmask, and a layer of sacrificial mandrel material, and removing portions of the layer of sacrificial mandrel material to expose portions of the second hardmask and form a first and second sacrificial mandrel. Spacers are formed adjacent to the sacrificial mandrels. A filler material is deposited on the second hardmask, and a first mask is formed on the filler material. An exposed portion of the second sacrificial mandrel is removed to form a first cavity. The depth of the first cavity is increased. The first mask, portions of the first and second sacrificial mandrels, the filler material, portions of the second hardmask, the spacers, portions of the planarization layer and the first hardmask are removed. A second cavity is formed and the first and second cavities are filled with a conductive material.Type: GrantFiled: August 15, 2017Date of Patent: May 15, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole Saulnier
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Publication number: 20180096846Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.Type: ApplicationFiled: October 4, 2016Publication date: April 5, 2018Inventors: John Christopher ARNOLD, Sean D. BURNS, Yann Alain Marcel MIGNOT, Yongan XU
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Patent number: 9934970Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.Type: GrantFiled: January 11, 2017Date of Patent: April 3, 2018Assignee: International Business Machines CorporationInventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
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Publication number: 20180076033Abstract: Multi-angled deposition and masking techniques are provided to enable custom trimming and selective removal of spacers that are used for patterning features at sub-lithographic dimensions. For example, a method includes forming a sacrificial mandrel on a substrate, and forming first and second spacers on opposing sidewalls of the sacrificial mandrel. The first and second spacers are formed with an initial thickness TS. A first angle deposition process is performed to deposit a material (e.g., insulating material or metallic material) at a first deposition angle A1 to form a first trim mask layer on an upper portion of the first spacer and the sacrificial mandrel while preventing the material from being deposited on the second spacer. A spacer etch process is performed to trim the first spacer to a first thickness T1, which is less than TS, using the first trim mask layer as an etch mask.Type: ApplicationFiled: September 9, 2016Publication date: March 15, 2018Inventors: Marc A. Bergendahl, Sean D. Burns, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
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Publication number: 20180076034Abstract: Multi-angled deposition and masking techniques are provided to enable custom trimming and selective removal of spacers that are used for patterning features at sub-lithographic dimensions. For example, a method includes forming a sacrificial mandrel on a substrate, and forming first and second spacers on opposing sidewalls of the sacrificial mandrel. The first and second spacers are formed with an initial thickness Ts. A first angle deposition process is performed to deposit a material (e.g., insulating material or metallic material) at a first deposition angle A1 to form a first trim mask layer on an upper portion of the first spacer and the sacrificial mandrel while preventing the material from being deposited on the second spacer. A spacer etch process is performed to trim the first spacer to a first thickness T1, which is less than Ts, using the first trim mask layer as an etch mask.Type: ApplicationFiled: November 13, 2017Publication date: March 15, 2018Inventors: Marc A. Bergendahl, Sean D. Burns, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
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Publication number: 20180076035Abstract: Multi-angled deposition and masking techniques are provided to enable custom trimming and selective removal of spacers that are used for patterning features at sub-lithographic dimensions. For example, a method includes forming a sacrificial mandrel on a substrate, and forming first and second spacers on opposing sidewalls of the sacrificial mandrel. The first and second spacers are formed with an initial thickness TS. A first angle deposition process is performed to deposit a material (e.g., insulating material or metallic material) at a first deposition angle A1 to form a first trim mask layer on an upper portion of the first spacer and the sacrificial mandrel while preventing the material from being deposited on the second spacer. A spacer etch process is performed to trim the first spacer to a first thickness T1, which is less than TS, using the first trim mask layer as an etch mask.Type: ApplicationFiled: November 13, 2017Publication date: March 15, 2018Inventors: Marc A. Bergendahl, Sean D. Burns, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
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Patent number: 9911647Abstract: A method for forming conductive lines on a wafer comprises forming a first hardmask, a planarizing layer, a second hardmask, a layer of sacrificial mandrel material on the second hardmask, and patterning a mask on the layer of sacrificial material. A first sacrificial mandrel and a second sacrificial mandrel and a gap are formed. A layer of spacer material is deposited in the gap. Portions of the first sacrificial mandrel and the second sacrificial mandrel are removed, and exposed portions of the second hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. The second hardmask, the spacers, and the planarizing layer are removed. Exposed portions of the insulator layer are removed to form a trench in the insulator layer, and the trench is filled with a conductive material.Type: GrantFiled: August 15, 2017Date of Patent: March 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sean D. Burns, Lawrence A. Clevenger, Anuja E. DeSilva, Nelson M. Felix, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
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Publication number: 20180025943Abstract: A method for forming conductive contacts on a wafer comprises forming a first hardmask, planarizing layer, second hardmask, and a layer of sacrificial mandrel material, and removing portions of the layer of sacrificial mandrel material to expose portions of the second hardmask and form a first and second sacrificial mandrel. Spacers are formed adjacent to the sacrificial mandrels. A filler material is deposited on the second hardmask, and a first mask is formed on the filler material. An exposed portion of the second sacrificial mandrel is removed to form a first cavity. The depth of the first cavity is increased. The first mask, portions of the first and second sacrificial mandrels, the filler material, portions of the second hardmask, the spacers, portions of the planarization layer and the first hardmask are removed. A second cavity is formed and the first and second cavities are filled with a conductive material.Type: ApplicationFiled: August 15, 2017Publication date: January 25, 2018Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole Saulnier
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Publication number: 20180005885Abstract: A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material.Type: ApplicationFiled: January 13, 2017Publication date: January 4, 2018Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A.M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
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Publication number: 20180005875Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: Sean D. Burns, Lawrence A. Clevenger, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Nicole Saulnier
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Patent number: 9852946Abstract: A method for forming conductive lines on a wafer comprises forming a first sacrificial mandrel and a second sacrificial mandrel. Spacers are formed adjacent to the first and second sacrificial mandrels. A filler material is deposited on the second hardmask. A first mask is formed on a portion of the second sacrificial mandrel. A first cavity and a second cavity are formed that expose portions of the second hardmask, and exposed portions of the second mask and exposed portions of the filler material are removed to expose portions of the first hardmask. Exposed portions of the first hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. Exposed portions of the insulator layer are removed to form a trench in the insulator layer and the trench is filled with a conductive material.Type: GrantFiled: June 8, 2016Date of Patent: December 26, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole Saulnier
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Publication number: 20170358492Abstract: A method for forming conductive lines on a wafer comprises forming a first sacrificial mandrel and a second sacrificial mandrel. Spacers are formed adjacent to the first and second sacrificial mandrels. A filler material is deposited on the second hardmask. A first mask is formed on a portion of the second sacrificial mandrel. A first cavity and a second cavity are formed that expose portions of the second hardmask, and exposed portions of the second mask and exposed portions of the filler material are removed to expose portions of the first hardmask. Exposed portions of the first hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. Exposed portions of the insulator layer are removed to form a trench in the insulator layer and the trench is filled with a conductive material.Type: ApplicationFiled: June 8, 2016Publication date: December 14, 2017Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole Saulnier
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Publication number: 20170358487Abstract: A method for forming conductive lines on a wafer comprises forming a first hardmask, a planarizing layer, a second hardmask, a layer of sacrificial mandrel material on the second hardmask, and patterning a mask on the layer of sacrificial material. A first sacrificial mandrel and a second sacrificial mandrel and a gap are formed. A layer of spacer material is deposited in the gap. Portions of the first sacrificial mandrel and the second sacrificial mandrel are removed, and exposed portions of the second hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. The second hardmask, the spacers, and the planarizing layer are removed. Exposed portions of the insulator layer are removed to form a trench in the insulator layer, and the trench is filled with a conductive material.Type: ApplicationFiled: August 15, 2017Publication date: December 14, 2017Inventors: Sean D. Burns, Lawrence A. Clevenger, Anuja E. DeSilva, Nelson M. Felix, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
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Publication number: 20170352585Abstract: An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a ? line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a ? line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an ? line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a ??? jog; a ??? jog; an ??? jog; a ??? jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.Type: ApplicationFiled: June 3, 2016Publication date: December 7, 2017Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann A.M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
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Patent number: 9786554Abstract: A method for forming conductive lines on a wafer comprises forming a first hardmask, a planarizing layer, a second hardmask, a layer of sacrificial mandrel material on the second hardmask, and patterning a mask on the layer of sacrificial material. A first sacrificial mandrel and a second sacrificial mandrel and a gap are formed. A layer of spacer material is deposited in the gap. Portions of the first sacrificial mandrel and the second sacrificial mandrel are removed, and exposed portions of the second hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. The second hardmask, the spacers, and the planarizing layer are removed. Exposed portions of the insulator layer are removed to form a trench in the insulator layer, and the trench is filled with a conductive material.Type: GrantFiled: June 8, 2016Date of Patent: October 10, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sean D. Burns, Lawrence A. Clevenger, Anuja E. DeSilva, Nelson M. Felix, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
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Patent number: 9779944Abstract: A method for manufacturing a semiconductor device includes forming a plurality of mandrels on a dielectric layer, conformally depositing a spacer layer on the plurality of mandrels, removing a portion of the spacer layer from a top surface of at least one of the plurality of mandrels, removing the at least one of the plurality of mandrels to create at least one opening, and filling the at least opening with a cut fill material, wherein the cut fill material comprises the same material as a material of the spacer layer.Type: GrantFiled: September 13, 2016Date of Patent: October 3, 2017Assignee: International Business Machines CorporationInventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Yann A. M. Mignot, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier