Abstract: Processing methods may be performed to form recesses in a semiconductor substrate. The methods may include oxidizing an exposed silicon surface on a semiconductor substrate within a processing region of a semiconductor processing chamber. The methods may include forming an inert plasma within the processing region of the processing chamber. Effluents of the inert plasma may be utilized to modify the oxidized silicon. A remote plasma may be formed from a fluorine-containing precursor to produce plasma effluents. The methods may include flowing the plasma effluents to the processing region of the semiconductor processing chamber. The methods may also include removing the modified oxidized silicon from the semiconductor substrate.

Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.

Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

Abstract: A method of processing a substrate includes depositing an oxide material on a substrate having a first region, a second region and a plurality of features, wherein the first region has a high feature density and the second region has a low feature density; and controlling a ratio of an etch rate of the oxide material in the first region to an etch rate of the oxide material in the second region by forming an ammonium hexafluorosilicate ((NH4)2SiF6) layer having a first thickness atop the oxide material in the first region and having a second thickness atop the oxide material in the second region.

Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.

Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

Abstract: A variable resistance memory device includes a plurality of first conductive layer pattern, a plurality of second conductive layer patterns over the first conductive layer patterns, and a plurality of lower cell structures including a switching element and a variable resistance element, the lower cell structures being formed at intersections at which the first conductive layer patterns and the second conductive layer patterns overlap each other. The first conductive layer patterns, the second conductive layer patterns and the lower cell structures serves as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure.

Abstract: In some embodiments methods of processing a substrate include: providing a substrate having a contact structure formed on the substrate, wherein the contact structure comprises a feature defined by gate structures, a silicon nitride layer disposed on a upper surface of the gate structures and on sidewalls and a bottom of the feature, and an oxide layer disposed over the silicon nitride layer and filling the feature; etching an opening through the oxide layer to the silicon nitride layer disposed on the bottom of the opening, wherein a width of the opening is less than a width of the feature; expanding the opening in the oxide layer to form a tapered profile; exposing the substrate to ammonia and nitrogen trifluoride to form an ammonium fluoride gas that forms an ammonium hexafluorosilicate film on the oxide layer; and heating the substrate to a second temperature to sublimate the ammonium hexafluorosilicate film.

Abstract: In some embodiments methods of processing a substrate include: providing a substrate having a contact structure formed on the substrate, wherein the contact structure comprises a feature defined by gate structures, a silicon nitride layer disposed on a upper surface of the gate structures and on sidewalls and a bottom of the feature, and an oxide layer disposed over the silicon nitride layer and filling the feature; etching an opening through the oxide layer to the silicon nitride layer disposed on the bottom of the opening, wherein a width of the opening is less than a width of the feature; expanding the opening in the oxide layer to form a tapered profile; exposing the substrate to ammonia and nitrogen trifluoride to form an ammonium fluoride gas that forms an ammonium hexafluorosilicate film on the oxide layer; and heating the substrate to a second temperature to sublimate the ammonium hexafluorosilicate film.

Abstract: A method of processing a substrate includes depositing an oxide material on a substrate having a first region, a second region and a plurality of features, wherein the first region has a high feature density and the second region has a low feature density; and controlling a ratio of an etch rate of the oxide material in the first region to an etch rate of the oxide material in the second region by forming an ammonium hexafluorosilicate ((NH4)2SiF6) layer having a first thickness atop the oxide material in the first region and having a second thickness atop the oxide material in the second region.

Abstract: Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer.

Abstract: Methods for processing a substrate include (a) providing a substrate comprising a silicon germanium layer and a patterned mask layer atop the silicon germanium layer to define a feature in the silicon germanium layer; (b) exposing the substrate to a first plasma formed from a first process gas to etch a feature into the silicon germanium layer; (c) subsequently exposing the substrate to a second plasma formed from a second process gas to form an oxide layer on a sidewall and a bottom of the feature; (d) exposing the substrate to a third plasma formed from a third process gas to etch the oxide layer from the bottom of the feature; and (e) repeating (b)-(d) to form the feature in the first layer to a desired depth, wherein the first process gas, the second process gas and the third process gas are not the same.

Abstract: Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer.

Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.

Abstract: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.

Abstract: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.

Abstract: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.

Abstract: This application discloses a hard disk drive comprising a landing ramp mounted to a disk base including a slider limiter for at least one slider in the hard disk drive to limit movement of the sliders during a non-operational shock event while parked on the loading ramp. Each of the slider limiters includes a clearance zone configured so that when the slider contacts the slider limiter during the non-operational event, the read-write head remains out of contact with the slider limiter. The clearance zone may include a recess and/or a cutout. The clearance zone may include a recess and/or a cutout. The recess may take any shape, for example the recess may be a polygon and/or curved in cross section. The polygon may have at least two sides. The clearance zone may further include a radial bulge to further protect the read-write head during non-operational shock events.