Patents by Inventor Sean Kang
Sean Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8165933Abstract: The present invention provides systems, methods, and computer program products for performing validation and clearance at a transaction item level for transaction received in a batch format. Each transaction of the batch is stored separately in a storage system, such as a logical database. Typically, image data and electronic data for a transaction are stored separately in the storage system and may be linked to each other. Each transaction is separately accessible and/or updateable. Each transaction stored in the storage system is separately analyzed to validate that the transaction is at least balanced. Transactions that determined to be balanced are cleared irrespective of a balance status associated with other transactions associated with the batch of transactions, such that transactions are individually cleared as opposed to being cleared in a batch format.Type: GrantFiled: May 23, 2008Date of Patent: April 24, 2012Assignee: Bank of America CorporationInventors: Eric Dryer, George Miller Abernethy, Ronald Hollander, Lowell Robert Huff, Sean Kang, Clarence E. Lee, Eric Scott Sandoz, Jeffrey Robert Woodside
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Patent number: 7892445Abstract: A method of dechucking a wafer, with a low-k dielectric layer, held onto an electrostatic chuck by an electrostatic charge in a plasma chamber is provided. The electrostatic clamping voltage is removed. An essentially argon free dechucking gas is provided into the plasma chamber. A dechucking plasma is formed from the dechucking gas in the plasma chamber. The dechucking plasma is stopped.Type: GrantFiled: September 12, 2007Date of Patent: February 22, 2011Assignee: Lam Research CorporationInventors: David Wei, Howard Dang, Masahiro Watanabe, Sean Kang, Kenji Takeshita, Mayumi Block, Stephen Sirard, Eric Hudson
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Publication number: 20100232070Abstract: This application discloses a hard disk drive comprising a landing ramp mounted to a disk base including a slider limiter for at least one slider in the hard disk drive to limit movement of the sliders during a non-operational shock event while parked on the loading ramp. Each of the slider limiters includes a clearance zone configured so that when the slider contacts the slider limiter during the non-operational event, the read-write head remains out of contact with the slider limiter. The clearance zone may include a recess and/or a cutout. The clearance zone may include a recess and/or a cutout. The recess may take any shape, for example the recess may be a polygon and/or curved in cross section. The polygon may have at least two sides. The clearance zone may further include a radial bulge to further protect the read-write head during non-operational shock events.Type: ApplicationFiled: March 11, 2009Publication date: September 16, 2010Inventors: Yao-Hsin Huang, Sean Kang, Bill Wang
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Patent number: 7782591Abstract: Particles are trapped away from a wafer transport zone in a chamber. A first electrode is on one side of the zone. A second electrode is on an opposite side of the zone. A power supply connected across the electrodes establishes an electrostatic field between the electrodes. The field traps particles at the electrodes, away from the zone. For transporting the wafer from the chamber, the second electrode mounts the wafer for processing, and the first electrode is opposite to the second electrode defining a process space. The zone is in the space with a separate part of the space separating the zone from each electrode. Particles are urged away from the wafer by simultaneously terminating plasma processing of the wafer, connecting the second electrode to ground, applying a positive DC potential to the first electrode, and de-chucking the wafer from the second electrode into the zone.Type: GrantFiled: June 22, 2007Date of Patent: August 24, 2010Assignee: Lam Research CorporationInventors: Sangjun Cho, Sean Kang, Tom Choi, Taejoon Han
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Publication number: 20090292628Abstract: The present invention provides systems, methods, and computer program products for performing validation and clearance at a transaction item level for transaction received in a batch format. Each transaction of the batch is stored separately in a storage system, such as a logical database. Typically, image data and electronic data for a transaction are stored separately in the storage system and may be linked to each other. Each transaction is separately accessible and/or updateable. Each transaction stored in the storage system is separately analyzed to validate that the transaction is at least balanced. Transactions that determined to be balanced are cleared irrespective of a balance status associated with other transactions associated with the batch of transactions, such that transactions are individually cleared as opposed to being cleared in a batch format.Type: ApplicationFiled: May 23, 2008Publication date: November 26, 2009Applicant: BANK OF AMERICA CORPORATIONInventors: Eric Dryer, George Miller Abernethy, Ronald Hollander, Lowell Robert Huff, Sean Kang, Clarence E. Lee, Eric Scott Sandoz, Jeffrey Robert Woodside
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Publication number: 20080314733Abstract: Particles are trapped away from a wafer transport zone in a chamber. A first electrode is on one side of the zone. A second electrode is on an opposite side of the zone. A power supply connected across the electrodes establishes an electrostatic field between the electrodes. The field traps particles at the electrodes, away from the zone. For transporting the wafer from the chamber, the second electrode mounts the wafer for processing, and the first electrode is opposite to the second electrode defining a process space. The zone is in the space with a separate part of the space separating the zone from each electrode. Particles are urged away from the wafer by simultaneously terminating plasma processing of the wafer, connecting the second electrode to ground, applying a positive DC potential to the first electrode, and de-chucking the wafer from the second electrode into the zone.Type: ApplicationFiled: June 22, 2007Publication date: December 25, 2008Applicant: LAM RESEARCH CORPORATIONInventors: Sangjun Cho, Sean Kang, Tom Choi, Taejoon Han
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Publication number: 20080293249Abstract: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.Type: ApplicationFiled: May 24, 2007Publication date: November 27, 2008Inventors: Sangjun Cho, Tom Choi, Taejoon Han, Sean Kang, Prabhakara Gopaladasu, Bi-Ming Yen
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Publication number: 20080278849Abstract: Disclosed is a hard disk drive that includes at least one disk enclosed by a cover and a disk. A damper is separated from the disk by an air gap about 1.0 mm. The damper and air gap reduce the velocity of the air flow and any vibration associated with the flow of air.Type: ApplicationFiled: May 7, 2007Publication date: November 13, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Haesung Kwon, Yun-Sik Han, Yanning Liu, Sean Kang, Hyung Jai Lee
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Publication number: 20080064214Abstract: In the fabrication of an integrated circuit where a porous silicon oxide layer is formed over a surface of a semiconductor substrate to electrically isolate two conductive metal layers, a via through the porous silicon oxide layer has an opening etched through the porous silicon oxide layer, a self-assembled monolayer adhering to an etched surface of the opening and to exposed pores, and a conductive material filling the opening.Type: ApplicationFiled: September 13, 2006Publication date: March 13, 2008Applicant: LAM RESEARCH CORPORATIONInventors: Taejoon Han, Sang-Jun Cho, Sung-Jin Cho, Tom Choi, Prabhakara Gopaladasu, Sean Kang
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Publication number: 20070293050Abstract: A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited over the sidewalls of the photoresist features to reduce the critical dimensions of the photoresist features. Features are etched into the layer, wherein the layer features have a second critical dimension, which is less than the first critical dimension.Type: ApplicationFiled: June 22, 2007Publication date: December 20, 2007Inventors: Sean Kang, Sangheon Lee, Wan-Lin Chen, Eric Hudson, S.M. Sadjadi, Gan Zhao
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Publication number: 20060011578Abstract: A method for etching a dielectric layer below a photoresist mask is provided. A wafer with the dielectric layer disposed below a photoresist mask is provided in an etch chamber. An etch gas comprising CF4 and H2 is provided into the etch chamber wherein the CF4 has a flow rate and the H2 has a flow rate, wherein the flow rate of H2 is greater than the flow rate of CF4. A plasma is formed from the etch gas. Features are etched into the dielectric layer through the etch mask using the plasma formed from the etch gas.Type: ApplicationFiled: July 16, 2004Publication date: January 19, 2006Inventors: Sean Kang, Zhisong Huang, S. M. Sadjadi
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Patent number: 6979579Abstract: In a plasma processing system, a method of inspecting a contact opening of a contact formed in a first layer of the substrate to determine whether the contact reaches a metal layer that is disposed below the first layer is shown. The method includes flowing a gas mixture into a plasma reactor of the plasma processing system, the gas mixture comprising a flow of a chlorine containing gas. The method also includes striking a plasma from the gas mixture; and exposing the contact to the plasma. The method further includes detecting whether metal chloride is present in the contact opening after the exposing.Type: GrantFiled: March 30, 2004Date of Patent: December 27, 2005Assignee: Lam Research CorporationInventors: Jisoo Kim, Sangheon Lee, Sean Kang, Binet Worsham, Bi-Ming Yen, Reza Sadjadi, Peter K. Loewenhardt
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Patent number: 6909195Abstract: The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.Type: GrantFiled: April 16, 2004Date of Patent: June 21, 2005Assignee: Lam Research CorporationInventors: SiYi Li, S. M. Reza Sadjadi, David R. Pirkle, Steve Lassig, Sean Kang, Vinay Pohray, Peter Cirigliano
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Publication number: 20050048785Abstract: A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited over the sidewalls of the photoresist features to reduce the critical dimensions of the photoresist features. Features are etched into the layer, wherein the layer features have a second critical dimension, which is less than the first critical dimension.Type: ApplicationFiled: August 26, 2003Publication date: March 3, 2005Inventors: Sean Kang, Sangheon Lee, Wan-Lin Chen, Eric Hudson, S. Sadjadi, Gan Zhao
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Publication number: 20050009324Abstract: The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.Type: ApplicationFiled: April 16, 2004Publication date: January 13, 2005Applicant: Lam Research CorporationInventors: SiYi Li, S.M. Sadjadi, David Pirkle, Stephan Lassig, Sean Kang, Vinay Pohray, Peter Cirigliano
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Patent number: 6794293Abstract: The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.Type: GrantFiled: October 5, 2001Date of Patent: September 21, 2004Assignee: Lam Research CorporationInventors: SiYi Li, S. M. Reza Sadjadi, David R. Pirkle, Steve Lassig, Sean Kang, Vinay Pohray, Peter Cirigliano
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Publication number: 20040038540Abstract: The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.Type: ApplicationFiled: October 5, 2001Publication date: February 26, 2004Applicant: Lam Research CorporationInventors: SiYi Li, S.M. Reza Sadjadi, David R. Pirkle, Stephan Lassig, Sean Kang, Vinay Pohray, Peter Cirigliano