Abstract: Methods to selectively form a dielectric etch stop layer over a patterned metal feature. Embodiments include a transistor incorporating such an etch stop layer over a gate electrode. In accordance with certain embodiments of the present invention, a metal is selectively formed on the surface of the gate electrode which is then converted to a silicide or germanicide. In other embodiments, the metal selectively formed on the gate electrode surface enables a catalytic growth of a silicon or germanium mesa over the gate electrode. At least a portion of the silicide, germanicide, silicon mesa or germanium mesa is then oxidized, nitridized, or carbonized to form a dielectric etch stop layer over the gate electrode only.

Abstract: A method for forming deep lithographic interconnects between a first metal and a second metal is provided. The method comprises depositing a first insulator layer on a semiconductor substrate; etching the first insulator layer at a selected location to provide at least a first via to the semiconductor substrate; depositing the first metal on the semiconductor substrate to form at least a first metal contact plug in the first via in contact with the semiconductor substrate; treating the semiconductor substrate with an in-situ plasma of a nitrogen containing gas wherein the plasma forms a nitride layer of the first metal at least capping a top surface of the first metal plug in the first via; and forming a second metal contact to the metal nitride layer capping at least the top surface of the first metal plug.

Abstract: In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed.

Abstract: Interconnect structures having improved adhesion and electromigration performance and methods to fabricate thereof are described. A tensile capping layer is formed on a first conductive layer on a substrate. A compressive capping layer is formed on the tensile capping layer. Next, an interlayer dielectric layer is formed on the compressive capping layer. Further, a first opening is formed in the ILD layer using a first chemistry. A second opening is formed in the tensile capping layer and the compressive capping layer using a second chemistry. Next, a second conductive layer is formed in the first opening and the second opening.

Abstract: Methods and apparatuses to selectively deposit a dielectric on a self-assembled monolayer (“SAM”) adsorbed metal are described. A wafer includes a device having a first electrode. A first self-assembled monolayer is deposited on the wafer covering the first electrode. Next, a portion of the first self-assembled monolayer is removed to expose the first electrode. The first self-assembled monolayer includes a hydrophobic layer. Further, second self-assembled monolayer is deposited on the first electrode. The second self-assembled monolayer includes a hydrophilic layer. Next, an insulating layer is deposited on the second self-assembled monolayer. Further, self-aligned contacts to one or more second electrodes of the device are formed.

Abstract: An apparatus for reducing amine poisoning of photoresist layers comprises a substrate, an etch stop layer containing amines formed over the substrate, and a dense capping layer formed directly on the etch stop layer, wherein the dense capping layer substantially prevents the amines from diffusing out of the etch stop layer and into a subsequently formed photoresist layer. The dense capping layer may comprise silicon carbide, silicon carboxide, or a combination of silicon carbide and silicon carboxide. The dense capping layer may have a density greater than or equal to 2 g/cm3 and a thickness that ranges from 10 ? to 200 ?.

Abstract: A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.

Abstract: A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.

Abstract: Embodiments of the invention provide a device with a hard mask layer between first and second ILD layers. The hard mask layer may have a k value approximately equal to the first and/or second ILD layers.