Abstract: A microcontroller has a numerical controlled oscillator receiving a primary clock signal and is configured to provide an internal system clock of the microcontroller. A method for operating a microcontroller performs the following steps: Selecting a primary clock signal from a plurality of clock signals; feeding the primary clock signal to a numerical controlled oscillator; configuring the numerical controlled oscillator to generate a numerical controlled clock signal; and providing the numerical controlled clock signal as an internal system clock for the microcontroller.

Abstract: A processor includes a RISC CPU core; and a plurality of peripherals including one or more configurable logic cell peripherals. The configurable logic cell peripheral may be configured to allow real-time software access to internal configuration and signals paths of the processor. The configurable logic cell peripheral may have real-time configuration control.

Abstract: A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.

Abstract: A microprocessor or microcontroller device may have a central processing unit (CPU), a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks, wherein a bank select register determines which memory bank is currently coupled with the CPU. Furthermore, a first and second set of special function registers are provided, wherein upon occurrence of a context switch either the first or the second set of special function register are selected as active context registers for the CPU and the respective other set of special function registers are selected as inactive context registers, wherein at least some of the registers of the active context registers are memory mapped to more than two memory banks of the data memory and wherein all registers of the inactive context registers are memory mapped to at least one memory location within the data memory.

Abstract: A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.

Abstract: An enhanced complementary waveform generator (ECWG) generates two complementary pulse width modulation (PWM) outputs determined by rising and falling event sources. In a simple configuration of the ECWG, the rising and falling event sources are the same signal which is a PWM signal having the desired period and duty cycle. The ECWG converts this single PWM input into dual complementary PWM outputs. The frequency and duty cycle of the dual PWM outputs substantially match those of the single input PWM signal. Blanking and deadband times may be introduced between the dual complementary PWM outputs, and the dual complementary PWM outputs may also be phase delayed.

Abstract: An enhanced complementary waveform generator (ECWG) generates two complementary pulse width modulation (PWM) outputs determined by rising and falling event sources. In a simple configuration of the ECWG, the rising and falling event sources are the same signal which is a PWM signal having the desired period and duty cycle. The ECWG converts this single PWM input into dual complementary PWM outputs. The frequency and duty cycle of the dual PWM outputs substantially match those of the single input PWM signal. Blanking and deadband times may be introduced between the dual complementary PWM outputs, and the dual complementary PWM outputs may also be phase delayed.

Abstract: An integrated circuit device inductive touch analog front end excites selected ones of a plurality of inductive touch sensors and provides analog output signals representative of voltages across the coils of the plurality of inductive touch sensors. Various characteristics of the inductive touch analog front end are programmable. A digital processor controls selection of each one of the plurality of inductive touch sensors and receives the respective analog output voltage signal from the inductive touch AFE. The digital processor may program the characteristics of the inductive touch analog front end. When a sufficient change in the coil voltage is determined by the digital processor, that inductive touch sensor is assumed to have been actuated and the digital processor takes action based upon which one of the plurality of inductive touch sensors was actuated (touched).

Abstract: An integrated circuit device has a modulator module that provides a modulation signal comprising one frequency keyed on and off, or alternating between two or more different frequencies or phases that are selected based upon a modulator signal. The one or more frequencies or phases may be selected from a plurality of frequency sources. Switching the one frequency on or off, or between the at least two different frequencies or phases may be synchronized with one or both of the two or more different frequencies or phases so that “glitches” or spurs are not introduced into the modulation signal. The integrated circuit device may also comprise a processor, memory, digital logic and input-output. Frequency sources may be internal to the digital device or external. The modulator signal may comprise serial data generated from the digital logic and/or processor of the digital device.

Abstract: A processor includes a RISC CPU core; and a plurality of peripherals including one or more configurable logic cell peripherals. The configurable logic cell peripheral may be configured to allow real-time software access to internal configuration and signals paths of the processor. The configurable logic cell peripheral may have real-time configuration control.

Abstract: An integrated circuit device, in accordance with embodiments as claimed includes a central processing core; and a plurality of peripherals operably coupled to the RISC CPU core. In some embodiments, the plurality of peripherals include at least one configurable logic cell peripheral having more inputs than input-output connections on the integrated circuit device. In some embodiments, the inputs include one or more inputs from one or more integrated circuit subsystems.

Abstract: A processor includes a RISC CPU core and a plurality of peripherals including a configurable logic cell peripheral. The configurable logic cell peripheral may be configured to combine a plurality of inputs into a single output. The configurable logic cell may be programmable to function as one of a plurality of predetermined logic functions.

Abstract: An apparatus for selecting a plurality of input signals from a plurality of y signals in a device has a switching matrix with a plurality of n to 1 mulitplexers, wherein each n to 1 multiplexer is assigned to a different input set of n of the y signals wherein a subset of less than n input signals of each set of input signals of each of the n to 1 multiplexers is also a subset of input signals of another n to 1 multiplexer.

Abstract: An integrated circuit device inductive touch analog front end (AFE) excites selected ones of a plurality of inductive touch sensors, measures voltages across the coils of the plurality of inductive touch sensors, and provides analog output signals representative of these coil voltages. A physical displacement (touch) to the inductive sensor causes the inductance value of the inductive touch sensor to change with a corresponding change in a voltage across the coil of the inductive touch sensor. A digital processor controls selection of each one of the plurality of inductive touch sensors and receives the respective analog output voltage signal from the inductive touch AFE. When a sufficient change in the coil voltage is determined by the digital processor, that inductive touch sensor is assumed to have been actuated and the digital processor takes action based upon which one of the plurality of inductive touch sensors was actuated (touched).

Abstract: A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area, wherein no consecutive memory block is formed by the second memory areas of a plurality of consecutive memory banks. An address adjustment unit is provided which, when a predefined address range is used, translates an address within the predefined address range to access said second memory areas such that through the address a plurality of second memory areas form a continuous linear memory block.

Abstract: An n-bit microprocessor device has an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, with at least two 16-bit indirect memory address registers which are accessible by the CPU across all banks; a bank access unit for coupling the CPU with one of the plurality of banks; a data memory coupled with the CPU; and a program memory coupled with the CPU, wherein the indirect address registers are operable to access the data memory or program memory and wherein a bit in each of the indirect memory address registers indicates an access to the data memory or to the program memory.

Abstract: An integrated circuit device provides a choice of external pins (connections) that may be user selectable for coupling an external filter/stabilization capacitor to an internal voltage regulator. However, connecting the output of a internal voltage regulator to an uncharged external filter/stabilization capacitor (or to a capacitor charged to a different voltage level than the internal regulation voltage) through a low impedance path can cause the regulator output voltage to sag/spike if the internal voltage regulator tries to charge/discharge the capacitor up/down to equilibrium with the regulator output voltage. To minimize this potential sag/spike, the voltage on the external filter/stabilization capacitor may be adjusted in a controlled manner to substantially the same voltage as the voltage on the output of the internal voltage regulator, and then the internal voltage regulator is operationally coupled through a low impedance to the external regulator filter/stabilization capacitor.

Abstract: A microcontroller has a data memory divided into a plurality of memory banks, an address multiplexer for providing an address to the data memory, an instruction register providing a first partial address to a first input of the address multiplexer, a bank select register which is not mapped to the data memory for providing a second partial address to a the first input of the address multiplexer, and a plurality of special function registers mapped to the data memory, wherein the plurality of special function registers comprises an indirect access register coupled with a second input of the address multiplexer, and wherein the data memory comprises more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped.

Abstract: An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped, a bank select register which is not mapped to the data memory for selecting a memory bank, and with an indirect access register mapped to at least one memory bank, wherein the instruction set includes a plurality of instructions operable to directly address all memory locations within a selected bank, at least one instruction that provides access to the bank select register, and at least one instruction performing an indirect address to the data memory using the indirect access register.

Abstract: An integrated circuit device has a modulator module that provides a modulation signal comprising one frequency keyed on and off, or alternating between two or more different frequencies or phases that are selected based upon a modulator signal. The one or more frequencies or phases may be selected from a plurality of frequency sources. Switching the one frequency on or off, or between the at least two different frequencies or phases may be synchronized with one or both of the two or more different frequencies or phases so that “glitches” or spurs are not introduced into the modulation signal. The integrated circuit device may also comprise a processor, memory, digital logic and input-output. Frequency sources may be internal to the digital device or external. The modulator signal may comprise serial data generated from the digital logic and/or processor of the digital device.