Patents by Inventor Sebastien Andre Jean
Sebastien Andre Jean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10790032Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.Type: GrantFiled: August 16, 2019Date of Patent: September 29, 2020Assignee: Micron Technology, Inc.Inventors: Greg A. Blodgett, Sebastien Andre Jean
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Patent number: 10747441Abstract: Devices and techniques for efficient allocation of storage connection resources are disclosed herein. An active trigger for a storage device is received when the storage device is in an idle state. A workload that corresponds to the storage device is measured to determine that the workload meets a threshold. Connection parameters, for a connection to the storage device, are negotiated based on the workload in response to receipt of the active trigger and the workload meeting the threshold. The workload is then executed on the storage device via the connection using the connection parameters.Type: GrantFiled: August 30, 2017Date of Patent: August 18, 2020Assignee: Micron Technology, Inc.Inventor: Sebastien Andre Jean
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Publication number: 20200218672Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to supply supported voltages to a host, provide temperature throttling information to the host, or provide an indication that a host attempting to read a result was not the host that caused the placement of the result in a result register. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.Type: ApplicationFiled: June 29, 2018Publication date: July 9, 2020Inventors: Greg A. Blodgett, Sebastien Andre Jean
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Patent number: 10699780Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.Type: GrantFiled: December 4, 2018Date of Patent: June 30, 2020Assignee: Micron Technology, Inc.Inventors: Sebastien Andre Jean, Ting Luo
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Publication number: 20200201551Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.Type: ApplicationFiled: March 2, 2020Publication date: June 25, 2020Inventor: Sebastien Andre Jean
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Publication number: 20200159426Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.Type: ApplicationFiled: January 27, 2020Publication date: May 21, 2020Inventors: Kulachet Tanpairoj, Sebastien Andre Jean, Kishore Kumar Muchherla, Ashutosh Malshe, Jianmin Huang
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Publication number: 20200133874Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.Type: ApplicationFiled: December 31, 2019Publication date: April 30, 2020Inventors: Carla L. Christensen, Jianmin Huang, Sebastien Andre Jean, Kulachet Tanpairoj
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Publication number: 20200135277Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.Type: ApplicationFiled: December 26, 2019Publication date: April 30, 2020Inventors: Ting Luo, Kulachet Tanpairoj, Harish Reddy Singidi, Jianmin Huang, Preston Allen Thomson, Sebastien Andre Jean
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Publication number: 20200125295Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A read request is received at a controller of a NAND device. Here, the read request includes a logical address and a physical address. A a verification component that corresponds to the physical address is retrieved a NAND array of the NAND device. A verification of the read request is computed using the logical address, the physical address, and the verification component. A read operation is then modified based on the verification.Type: ApplicationFiled: September 24, 2019Publication date: April 23, 2020Inventor: Sebastien Andre Jean
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Patent number: 10579288Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.Type: GrantFiled: August 31, 2017Date of Patent: March 3, 2020Assignee: Micron Technology, Inc.Inventor: Sebastien Andre Jean
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Patent number: 10572388Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.Type: GrantFiled: August 30, 2017Date of Patent: February 25, 2020Assignee: Micron Technology, Inc.Inventors: Carla L. Christensen, Jianmin Huang, Sebastien Andre Jean, Kulachet Tanpairoj
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Patent number: 10559369Abstract: Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage event. A history of voltage events is modified with the voltage event. A voltage condition is observed from the history of voltage events. An operational parameter of a NAND array in the NAND device is then modified in response to the voltage condition.Type: GrantFiled: May 7, 2019Date of Patent: February 11, 2020Assignee: Micron Technology, Inc.Inventors: Sebastien Andre Jean, Harish Reddy Singidi
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Publication number: 20200043559Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.Type: ApplicationFiled: August 16, 2019Publication date: February 6, 2020Inventors: Greg A. Blodgett, Sebastien Andre Jean
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Publication number: 20200035314Abstract: Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.Type: ApplicationFiled: October 1, 2019Publication date: January 30, 2020Inventor: Sebastien Andre Jean
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Patent number: 10545685Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.Type: GrantFiled: August 30, 2017Date of Patent: January 28, 2020Assignee: Micron Technology, Inc.Inventors: Kulachet Tanpairoj, Sebastien Andre Jean, Kishore Kumar Muchherla, Ashutosh Malshe, Jianmin Huang
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Publication number: 20200004689Abstract: Devices and techniques for memory constrained translation table management are disclosed herein. A level of a translation table is logically segmented into multiple segments. Here, a bottom level of the translation table includes a logical to physical address pairing for a portion of a storage device and other levels of the translation table include references within the translation table. The multiple segments are written to the storage device. A first segment of the multiple segments is loaded to byte-addressable memory. A request for an address translation is received and determined to be for an address referred to by a second segment of the multiple segments. The first segment is then replaced with the second segment in the byte-addressable memory and the request is fulfilled using the second segment to locate a lower level of the translation table that includes the address translation.Type: ApplicationFiled: September 12, 2019Publication date: January 2, 2020Inventor: Sebastien Andre Jean
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Patent number: 10522229Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.Type: GrantFiled: August 30, 2017Date of Patent: December 31, 2019Assignee: Micron Technology, Inc.Inventors: Ting Luo, Kulachet Tanpairoj, Harish Singidi, Jianmin Huang, Preston Thomson, Sebastien Andre Jean
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Publication number: 20190361812Abstract: Disclosed in some examples are methods, systems, and machine readable mediums that dynamically adjust the size of an L2P cache in a memory device in response to observed operational conditions. The L2P cache may borrow memory space from a donor memory location, such as a read or write buffer. For example, if the system notices a high amount of read requests, the system may increase the size of the L2P cache at the expense of the write buffer (which may be decreased). Likewise, if the system notices a high amount of write requests, the system may increase the size of the L2P cache at the expense of the read buffer (which may be decreased).Type: ApplicationFiled: August 7, 2019Publication date: November 28, 2019Inventor: Sebastien Andre Jean
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Patent number: 10453543Abstract: Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.Type: GrantFiled: October 31, 2017Date of Patent: October 22, 2019Assignee: Micron Technology, Inc.Inventor: Sebastien Andre Jean
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Patent number: 10437734Abstract: Devices and techniques for memory constrained translation table management are disclosed herein. A level of a translation table is logically segmented into multiple segments. Here, a bottom level of the translation table includes a logical to physical address pairing for a portion of a storage device and other levels of the translation table include references within the translation table. The multiple segments are written to the storage device. A first segment of the multiple segments is loaded to byte-addressable memory. A request for an address translation is received and determined to be for an address referred to by a second segment of the multiple segments. The first segment is then replaced with the second segment in the byte-addressable memory and the request is fulfilled using the second segment to locate a lower level of the translation table that includes the address translation.Type: GrantFiled: August 31, 2017Date of Patent: October 8, 2019Assignee: Micron Technology, Inc.Inventor: Sebastien Andre Jean