Abstract: Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage event. A history of voltage events is modified with the voltage event. A voltage condition is observed from the history of voltage events. An operational parameter of a NAND array in the NAND device is then modified in response to the voltage condition.

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.

Abstract: Devices and techniques for implementing quality-of-service (QoS) parameters in a managed memory device having a number of memory dies are disclosed herein. A memory controller can receive instructions from a host device, determine an initial priority for each instruction using QoS parameters, and allocate the received instructions to the number of memory dies using the initial priority. The memory controller can maintain separate schedules for each of the number or memory dies, update the initial priority for each instruction with the separate schedules, and maintain each of the separate schedules using the updated priority for each instruction in the respective separate schedule.

Abstract: Devices and techniques for memory constrained translation table management are disclosed herein. A level of a translation table is logically segmented into multiple segments. Here, a bottom level of the translation table includes a logical to physical address pairing for a portion of a storage device and other levels of the translation table include references within the translation table. The multiple segments are written to the storage device. A first segment of the multiple segments is loaded to byte-addressable memory. A request for an address translation is received and determined to be for an address referred to by a second segment of the multiple segments. The first segment is then replaced with the second segment in the byte-addressable memory and the request is fulfilled using the second segment to locate a lower level of the translation table that includes the address translation.

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Abstract: Devices and techniques for increased NAND performance under high thermal conditions are disclosed herein. An indicator of a high-temperature thermal condition for a NAND device may be obtained. A workload of the NAND device may be measured in response to the high-temperature thermal condition. Operation of the NAND device may then be modified based on the workload and the high-temperature thermal condition.

Abstract: Apparatus and methods are disclosed including a memory device or a memory controller configured to receive, from a host device over a host interface, a request for a device descriptor of a memory device, and to send to the host, over the host interface, the device descriptor, the device descriptor including voltage supply capability fields that are set to indicate supported voltages of the memory device, the supported voltages selected from a plurality of discrete voltages. The host device can utilize the supported voltages to supply an appropriate voltage to the memory device. Methods of operation are disclosed, as well as machine-readable medium, a host computing device, and other embodiments.

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

Abstract: Devices and techniques to reduce corruption of preloaded data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, up to a threshold amount on a memory array in a reflow-protection mode, and to transition from the reflow-protection mode to a normal-operation mode after the initial data exceeds the threshold amount.

Abstract: Apparatus and methods are disclosed, including identifying and tagging data in a group of volatile memory cells of a host device to be written to and maintained contiguously on non-volatile memory of a storage system, and writing the tagged data to the group of non-volatile memory cells. A host device includes a host processor and the group of volatile memory cells, and a storage system includes the group of non-volatile memory cells.

Abstract: Apparatus and methods are disclosed, including identifying inactive data in a group of volatile memory cells of a host device, assembling identified inactive data in an offload unit of the group of volatile memory cells, and writing the offload unit of inactive data to a group of non-volatile memory cells of a storage system when the amount of inactive data in the offload unit reaches a threshold.

Abstract: Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.

Abstract: Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage event. A history of voltage events is modified with the voltage event. A voltage condition is observed from the history of voltage events. An operational parameter of a NAND array in the NAND device is then modified in response to the voltage condition.

Abstract: Methods, systems, and computer readable media for providing a flexible host memory buffer are disclosed. One method includes allocating an amount of host memory as a host memory buffer accessible by a solid state drive (SSD) as a cache for SSD data. The method further includes caching data from the solid state drive in the host memory buffer. The method further includes monitoring utilization of the host memory buffer. The method further includes dynamically increasing or decreasing the amount of host memory allocated for the host memory buffer based on the utilization.

Abstract: Methods, systems, and computer readable media for providing a flexible host memory buffer are disclosed. One method includes allocating an amount of host memory as a host memory buffer accessible by a solid state drive (SSD) as a cache for SSD data. The method further includes caching data from the solid state drive in the host memory buffer. The method further includes monitoring utilization of the host memory buffer. The method further includes dynamically increasing or decreasing the amount of host memory allocated for the host memory buffer based on the utilization.